CIRCULAR WEAR LEVELING

• US 20090259801A1
• Filed: 04/15/2008
• Published: 10/15/2009
• Est. Priority Date: 04/15/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Inventors: Ellis, Robert W., Fitzgerald, Alan A., Kilzer, Kevin L., Sterbenz, Rudolph J.
• Granted Patent: US 8,028,123 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 16/1724 Details of de-fragmentation performed by the file system saving storage space on storage systems G06F3/0608; management of blocks in storage devices G06F3/064
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for flash memory management comprises providing a head pointer configured to define a first location in a flash memory, and a tail pointer configured to define a second location in a flash memory. The head pointer and tail pointer define a payload data area. Payload data is received from a host, and written to the flash memory in the order it was received. The head pointer and tail pointer are updated such that the payload data area moves in a circular manner within the flash memory.

Claims

1. A method for flash memory management, comprising:

providing a head pointer configured to define a first location in a flash memory;

providing a tail pointer configured to define a second location in the flash memory, wherein the head pointer and tail pointer define the beginning and end of a payload data area, respectively;

receiving payload data from a host;

writing the payload data to the flash memory in the order the payload data was received from the host, and

updating the head pointer and tail pointer such that the payload data area moves in a circular manner within the flash memory.

2. The method of claim 1, wherein updating the head pointer and tail pointer causes the flash memory to wear substantially uniformly.

3. The method of claim 1, further comprising a second head pointer and second tail pointer such that two payload data areas move in a circular manner within the flash memory.

4. The method of claim 1, wherein receiving payload data from a host is performed in a manner compatible with at least one of PATA, SATA, SCSI, Fibre Channel, USB, IEEE 1394, and SAS protocols.

5. The method of claim 1, further comprising providing at least one data structure configured to locate payload data written to the flash memory.

6. The method of claim 5, wherein the at least one data structure is contained entirely in random access memory.

7. A method for data management on a flash memory device, comprising:

defining a circular storage space comprised of erase blocks;

receiving payload data from a host; and

writing the payload data in the order it was received from the host to at least one erase block in the circular storage space.

8. The method of claim 7, further comprising relocating at least a portion of existing payload data in the circular storage space such that existing payload data is stored substantially contiguously in the circular storage space.

9. The method of claim 8, wherein relocating existing payload data comprises operations on erase blocks located behind a head pointer and ahead of a tail pointer.

10. The method of claim 8, wherein relocating existing payload data comprises operations on erase blocks located ahead of a head pointer.

11. The method of claim 8, wherein relocating existing payload data comprises merging at least two partially obsolete erase blocks into a single erase block.

12. The method of claim 7, further comprising providing at least one data structure configured to locate payload data written to the at least one erase block.

13. The method of claim 12, wherein the at least one data structure is contained entirely in random access memory.

14. A solid state drive, comprising:

a flash memory controller configured to receive payload data from a host; and

at least one flash chip configured as a circular storage space, wherein the flash memory controller is configured to write the payload data to the at least one flash chip in the order it was received from the host.

15. The solid state drive of claim 14, wherein the flash memory controller comprises at least two head pointers such that consecutively received pages of payload data are stored in different erase blocks in the circular storage space.

16. The solid state drive of claim 14, wherein the host interface is at least one of PATA, SATA, SCSI, Fibre Channel, USB, IEEE 1394, and SAS.

17. The solid state drive of claim 14, wherein the flash memory controller comprises software installed on a host computer.

18. The solid state drive of claim 14, further comprising at least one data structure configured to locate payload data written to the at least one flash chip.

19. The solid state drive of claim 18, wherein the at least one data structure is contained entirely in random access memory.

20. A data storage system, comprising:

a flash memory configured as a circular storage space; and

a flash controller coupled to the flash memory, wherein the flash controller is configured to write incoming data to the flash memory in the order the data is received.

21. The data storage system of claim 20, further comprising a host interface to a host computer, wherein said host interface is configured to be compatible with at least one of PATA, SATA, SCSI, Fibre Channel, USB, IEEE 1394, and SAS.

22. The data storage system of claim 20, wherein the flash controller comprises driver software installed on a host computer.

23. The data storage system of claim 20, further comprising at least one data structure configured to locate data written to the flash memory.

24. The data storage system of claim 23, wherein the at least one data structure is contained entirely in random access memory.