FLASH MANAGEMENT USING BAD PAGE TRACKING AND HIGH DEFECT FLASH MEMORY

• US 20090259806A1
• Filed: 04/15/2009
• Published: 10/15/2009
• Est. Priority Date: 04/15/2008
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: ADTRAN Incorporated (ADTRAN Holdings, Inc.)
• Inventors: Ellis, Robert W., Kilzer, Kevin L., Sterbenz, Rudolph J.
• Application Number:
  US12/424,464
• Publication Number:
  US 20090259806A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Disclosed are techniques for flash memory management, including utilizing defect information corresponding to a granularity smaller than a physical erase block size of a flash memory chip.

Claims

1. A method for flash memory management, comprising:

storing defect information for one or more erase blocks in a flash memory; and

constructing a data table associated with the flash memory, wherein entries of the data table correspond to physical portions within the flash memory, wherein the size of the physical portions is smaller than the size of an erase block in the flash memory, and wherein entries of the data table comprise defect information associated with the physical portions.

2. The method of claim 1, wherein the data table is constructed responsive to the flash memory being powered on.

3. The method of claim 1, wherein the data table is a defect list.

4. The method of claim 1, wherein entries of the data table correspond to logical pages within the flash memory.

5. The method of claim 4, wherein the size of the logical pages is smaller than the size of a physical page in the flash memory.

6. The method of claim 5, further comprising updating the data table responsive to payload data being stored in at least one logical page within the flash memory, wherein the payload data is written to the flash memory in the order it was received from a host.

7. The method of claim 6, wherein writing the payload data in the order it was received further comprises writing the payload data in a sequential manner within at least one erase block in the flash memory.

8. The method of claim 6, wherein the contents of the data table reflect that there is no ordinal relationship among payload data stored in physical pages in an erase block in the flash memory.

9. The method of claim 1, further comprising storing the data table entirely in random access memory in a solid state drive.

10. The method of claim 1, wherein storing defect information comprises storing, in an erase block in the flash memory, defect information associated with a different erase block in the flash memory.

11. The method of claim 1, wherein the flash memory comprises at least two flash memory chips having different storage capacities.

12. The method of claim 1, wherein the flash memory comprises a flash chip, and wherein more than 2 percent of the erase blocks within the flash chip are marked as unusable by the flash chip manufacturer.

13. The method of claim 1, wherein the flash memory comprises a flash chip, and wherein more than 2 percent of the erase blocks within the flash chip contain at least one inoperative memory element.

14. A data storage system, comprising:

a memory configured for block-based erase operations;

a controller in communication the memory, wherein the controller is configured to write incoming data to the memory in the order the data is received; and

a data table in communication with the controller, wherein entries of the data table correspond to physical portions within the memory, wherein the size of the physical portions is smaller than the size of an erase block in the memory, and wherein entries of the data table comprise defect information associated with the physical portions.

15. The data storage system of claim 14, wherein the controller comprises a buffer-host machine, a media-buffer machine, a data buffer, a local buffer, and a sequence and control machine.

16. The data storage system of claim 14, wherein the controller is configured to write incoming payload data in a sequential manner within an erase block in the memory.

17. The data storage system of claim 14, wherein entries of the data table correspond to logical pages within the memory, and wherein the size of the logical pages is smaller than the size of a physical page in the memory.

18. The method of claim 17, further comprising updating the data table responsive to payload data being stored in at least one logical page within the memory, wherein the payload data is written to the memory in the order it was received from a host.

19. A tangible computer-readable medium having instructions stored thereon, the instructions comprising:

instructions to store defect information for one or more erase blocks in a flash memory; and

instructions to construct a data table associated with the flash memory, wherein entries of the data table correspond to physical portions within the flash memory, wherein the size of the physical portions is smaller than the size of an erase block in the flash memory, and wherein entries of the data table comprise defect information associated with the physical portions.

20. A method for reclaiming unused memory in a flash chip, the method comprising:

testing the flash chip to identify physical pages having an inoperative memory element therein, wherein the flash chip comprises erase blocks, and wherein the flash chip is configured with a list identifying one or more of the erase blocks as unusable;

constructing a data table associated with the flash chip, wherein entries of the data table correspond to physical pages within the flash chip, wherein the size of the physical pages is smaller than the size of an erase block in the flash chip, and wherein entries of the data table comprise defect information associated with the physical pages; and

storing payload data in a physical page within an erase block in the flash chip, wherein the erase block was identified on the list of unusable erase blocks.

21. The method of claim 20, wherein the list identifies at least 2 percent of the total erase blocks in the flash chip.

22. The method of claim 20, wherein the list identifying unusable erase blocks is provided by the flash chip manufacturer.

23. The method of claim 20, wherein the erase blocks identified as unusable comprise more than X percent of the total memory elements in the flash chip, and wherein more than 100−

X percent of the total memory elements in the flash chip are available for storing data.