PROCESS FOR THE VERTICAL INTERCONNECTION OF 3D ELECTRONIC MODULES BY VIAS

• US 20090260228A1
• Filed: 10/24/2008
• Published: 10/22/2009
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: 3D Plus
• Original Assignee: 3D Plus
• Inventors: Val, Christian
• Granted Patent: US 8,567,051 B2
• Time in Patent Office: Days
• US Class Current: 29/830
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68368 used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01058 : Cerium [Ce]
• CPC Class Codes: H01L 2924/01061 : Promethium [Pm]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49165 : by forming conductive walled aperture in base

Abstract

The present invention relates to a process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack, which comprises steps consisting in:

• • A) fabricating a batch of wafer levels (19) comprising n geometric features bounded by dicing lines (14), each feature being provided with at least one electronic component (6) surrounded by insulating resin (9) and connected to electrical connection pads (4), the pads being connected to electrical connection tracks (12) deposited on a dielectric layer (11); each track (12) extends as far as an electrode (13) interconnecting the tracks and located on the dicing lines (14), and comprises a curved segment (12a) defining a zone (15a) that surrounds a location intended to form a via,
  • B) stacking and assembling the K wafer levels (19) so as to superpose said zones (15a);
  • C) drilling vias (15) in the resin (9) plumb with the locations of the vias,
  • D) metallizing the wall of the vias (15) by electrolytic growth; and
  • E) cutting the stack along the dicing lines (14), the width of the cuts being greater than that of the electrode (13), so as to obtain the 3D electronic modules (100).

Claims

1. Process for the vertical interconnection of n 3D electronic modules, n being an integer greater than 1, a module comprising a stack of K electronic wafer levels, a wafer level i, i varying from 1 to K, comprising at least one electronic component, the K wafer levels being electrically connected together by conductors lying along the direction of the stack, and comprises a first step consisting, for each wafer level i, of:

A) a step of fabricating a batch of n wafer levels, a wafer level comprising at least n geometric features bounded by dicing lines, each feature being provided with at least one electronic component surrounded by insulating resin and connected to electrical connection pads, the pads being connected to electrical connection tracks deposited on a dielectric layer, wherein each track extends as far as an electrode interconnecting the tracks and located on the dicing lines, and comprises a curved segment placed between two straight segments, the curved segment defining a zone that surrounds a location intended to form a via, this zone being placed between the connection pad and the track interconnection electrode, and a second step consisting in;

B) stacking and assembling the K wafer levels obtained after the first step so as to superpose said zones approximately one on top of another;

C) drilling vias in the resin along the direction of the stack and over the entire thickness of the latter plumb with the locations of the vias, the cross section of the vias being such that, for each wafer level, the straight segments are flush with the vias but not with the curved segments;

D) metallizing the wall of the vias by electrolytic growth; and

E) cutting the stack along the dicing lines, the width of the cuts being greater than that of the electrode, so as to obtain the n 3D electronic modules.

2. Process according to the preceding claim, wherein the metal of the vias is copper or nickel or gold or silver or tin.

3. Process according to claim 1, wherein at least one of the straight segments has a protrusion inside said zone.

4. Process according to claim 1, wherein that the curved segment is a circular arc or a circle, an elliptical arc or an ellipse, a half-triangle or a triangle, or a half-rectangle or a rectangle.

5. Process according to claim 1, wherein the electronic component is an active or passive component or a MEMS.

6. Process according to claim 1, wherein at least one passive component is located in the wafer or on the wafer.

7. Process according to claim 1, wherein the vias are formed by laser dry etching or plasma dry etching.

8. Process according to claim 1, wherein the vias are formed by wet etching.