LOW TEMPERATURE THIN FILM TRANSISTOR PROCESS, DEVICE PROPERTY, AND DEVICE STABILITY IMPROVEMENT

• US 20090261331A1
• Filed: 04/16/2009
• Published: 10/22/2009
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Park, Beom Soo, Choi, Soo Young, Won, Tae Kyung, White, John M., Yang, Ya-Tang
• Granted Patent: US 8,110,453 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A method and apparatus for forming a thin film transistor is provided. A gate dielectric layer is formed, which may be a bilayer, the first layer deposited at a low rate and the second deposited at a high rate. In some embodiments, the first dielectric layer is a silicon rich silicon nitride layer. An active layer is formed, which may also be a bilayer, the first active layer deposited at a low rate and the second at a high rate. The thin film transistors described herein have superior mobility and stability under stress.

Claims

1. A method of forming a thin film transistor, comprising:

forming a silicon-rich silicon nitride layer over a substrate at a first rate;

forming a silicon nitride layer over the silicon-rich silicon nitride layer at a second rate;

forming a first amorphous silicon layer over the silicon nitride layer at a third rate; and

forming a second amorphous silicon layer over the first amorphous silicon layer at a fourth rate.

2. The method of claim 1, wherein the second rate is less than the first rate.

3. The method of claim 1, wherein the third rate is less than the fourth rate.

4. The method of claim 1, wherein the silicon-rich silicon nitride layer has a silicon to nitrogen ratio greater than about 0.83:

1.

5. The method of claim 1, wherein the silicon-rich silicon nitride layer has a silicon to hydrogen bond content between about 18 atomic percent and about 30 atomic percent.

6. The method of claim 1, wherein the silicon-rich silicon nitride layer is thicker than the silicon nitride layer.

7. The method of claim 1, wherein the second amorphous silicon layer is thicker than the first amorphous silicon layer.

8. The method of claim 2, wherein the silicon-rich silicon nitride layer has a silicon to nitrogen ratio greater than about 0.83:

1.

9. A method of forming a thin film transistor, comprising:

forming a silicon-rich silicon nitride layer on a substrate at a first rate to a first thickness;

forming a bottom gate layer comprising metal over the silicon-rich silicon nitride layer;

forming a silicon nitride layer over the bottom gate layer at a second rate to a second thickness;

forming a first amorphous silicon layer over the silicon nitride layer at a third rate to a third thickness;

forming a second amorphous silicon layer over the first amorphous silicon layer at a fourth rate to a fourth thickness;

forming a doped silicon containing layer over the second amorphous silicon layer to a fifth thickness; and

forming a conductive contact layer over the doped silicon containing layer.

10. The method of claim 9, wherein the second rate is less than the first rate and the third rate is less than the fourth rate.

11. The method of claim 9, wherein the second thickness is less than the first thickness and the third thickness is less than the fourth thickness.

12. The method of claim 9, wherein the silicon-rich silicon nitride layer and the silicon nitride layer are deposited in the same chamber.

13. The method of claim 12, wherein the silicon-rich silicon nitride layer has a silicon to nitrogen ratio greater than about 0.83:

1.

14. The method of claim 13, wherein the silicon-rich silicon nitride layer has a silicon to hydrogen bond content between about 18 atomic percent and about 30 atomic percent.

15. A thin-film transistor, comprising:

a silicon-rich silicon nitride layer having a first thickness disposed over a substrate;

a silicon nitride layer having a second thickness less than the first thickness disposed over the silicon-rich silicon nitride layer;

a first amorphous silicon layer having a third thickness disposed over the silicon nitride layer;

a second amorphous silicon layer having a fourth thickness disposed over the first amorphous silicon layer;

a doped silicon-containing layer disposed over the second amorphous silicon layer;

a conductive layer disposed over the doped silicon-containing layer; and

a passivation layer disposed over the conductive layer.

16. The transistor of claim 15, wherein the silicon-rich silicon nitride layer has a refractive index between about 1.92 and about 1.96.

17. The transistor of claim 15, wherein the silicon-rich silicon nitride layer has a silicon:

nitrogen ratio greater than about 0.85;

1.

18. The transistor of claim 15, wherein the silicon-rich silicon nitride layer and the silicon nitride layer are deposited in the same process chamber.

19. The transistor of claim 15, wherein the content of Si—

H bonds in the silicon-rich silicon nitride layer is between about 21 atomic percent and about 27 atomic percent.

20. The transistor of claim 15, wherein the silicon-rich silicon nitride layer, the silicon nitride layer, the first amorphous silicon layer, and the second amorphous silicon layer are formed at a temperature less than about 250°

C.