Integrating CMOS and Optical Devices on a Same Chip

• US 20090261346A1
• Filed: 05/27/2008
• Published: 10/22/2009
• Est. Priority Date: 04/16/2008
• Status: Abandoned Application

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chen, Ding-Yuan
• Application Number:
  US12/127,569
• Publication Number:
  US 20090261346A1
• Time in Patent Office: Days
• US Class Current: 257/76
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/15 including semiconductor components having potential barriers, specially adapted for light emission
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

An integrated circuit structure includes a semiconductor substrate having a first surface region and a second surface region, wherein the first surface region and the second surface region have different surface orientations; a semiconductor device formed at a surface of the first surface region; and a group-III nitride layer over the second surface region, wherein the group-III nitride layer does not extend over the first surface region.

Claims

1. An integrated circuit structure comprising:

a semiconductor substrate having a first surface region and a second surface region, wherein the first surface region and the second surface region have different surface orientations;

a semiconductor device formed at a surface of the first surface region; and

a group-III nitride layer over the second surface region, wherein the group-III nitride layer does not extend over the first surface region.

2. The integrated circuit structure of claim 1, wherein the semiconductor device comprises a CMOS device.

3. The integrated circuit structure of claim 2, wherein the CMOS device is an electro-static discharge (ESD) device.

4. The integrated circuit structure of claim 2, wherein the CMOS device is a driver circuit.

5. The integrated circuit structure of claim 1, wherein the semiconductor device comprises a diode.

6. The integrated circuit structure of claim 1, wherein the first surface region has a surface orientation selected from the group consisting essentially of a (100) surface orientation and a (110) surface orientation, and the second surface region has a (111) surface orientation.

7. The integrated circuit structure of claim 6, wherein the first surface region has the (100) surface orientation.

8. The integrated circuit structure of claim 1, wherein the group-III nitride layer comprises gallium nitride (GaN).

9. The integrated circuit structure of claim 1 further comprising a light-emitting diode over the group-III nitride layer.

10. The integrated circuit structure of claim 1 further comprising a high-power microwave high electron mobility transistor (HEMT) over the group-III nitride layer.

11. An integrated circuit structure comprising:

a semiconductor chip comprising;

a silicon substrate having a (100) surface orientation;

a first surface region on the silicon substrate, wherein the first surface region comprises crystalline silicon having a (100) surface orientation;

a second surface region on the silicon substrate, wherein the second surface region comprises crystalline silicon having a (111) surface orientation;

a complementary metal-oxide-semiconductor (CMOS) device at a top surface of the first surface region; and

an optical device over the second surface region.

12. The integrated circuit structure of claim 11, wherein top surfaces of the first and the second surface regions are substantially leveled.

13. The integrated circuit structure of claim 11 further comprising a gallium nitride (GaN) layer on the second surface region, and a light-emitting diode on the GaN layer.

14. The integrated circuit structure of claim 11, wherein the second surface region comprises silicon carbon.

15. An integrated circuit structure comprising:

a silicon substrate;

a first surface region on the silicon substrate, wherein the first surface region comprises crystalline silicon having a (100) surface orientation;

a second surface region of the silicon substrate, wherein the second surface region comprises crystalline silicon having a (111) surface orientation;

a complementary metal-oxide-semiconductor (CMOS) circuit at a top surface of the first surface region;

a gallium nitride (GaN) layer over the second surface region; and

an optical device over the GaN layer.

16. The integrated circuit structure of claim 15, wherein the optical device is a light-emitting diode.

17. The integrated circuit structure of claim 15, wherein the CMOS circuit is an electro-static discharge (ESD) circuit.

18. The integrated circuit structure of claim 15, wherein the second surface region comprises silicon carbon.