CMOS integrated process for fabricating monocrystalline silicon micromechanical elements by porous silicon micromachining

• US 20090261387A1
• Filed: 12/12/2008
• Published: 10/22/2009
• Est. Priority Date: 06/13/2006
• Status: Active Grant

• Current Assignee: Mta Muszaki Fizikai Es Anyagtudomanyi Kutatointezet
• Original Assignee: Mta Muszaki Fizikai Es Anyagtudomanyi Kutatointezet
• Inventors: Barsony, Istvan, Adam, Antalne, Mohacsy, Tibor, Vazsonyi, Eva, Payer, Karolyne, Ducso, Csaba, Eros, Magdolna
• Granted Patent: US 8,115,240 B2
• Time in Patent Office: Days
• US Class Current: 257/254
• CPC Class Codes: B81B 2201/0264 Pressure sensors
• CPC Class Codes: B81B 2201/0292 Sensors not provided for in B81B2201/0207 - B81B2201/0285
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2201/0115 Porous silicon
• CPC Class Codes: B81C 2203/0714 Forming the micromechanical structure with a CMOS process
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit
• CPC Class Codes: G01L 5/228 using tactile array force sensors
• CPC Class Codes: Y10T 29/42 Piezoelectric device making

Abstract

The invention relates to a process for fabricating a monocrystalline Si-micromechanical element integrated with a CMOS circuit element within the CMOS technology, wherein a domain of second conducting property is formed within a substrate of first conducting property, here the second conducting property is reverse with respect to the first conducting property, then simultaneously with or immediately after this a domain of monocrystalline Si is formed within the substrate for fabricating a micromechanical element. After this, a CMOS circuit element is fabricated within the substrate through the known steps of CMOS technology and then the circuit element, as well as a portion of said domain for fabricating the micromechanical element that will carry the micromechanical element after its fabrication are covered with a protecting layer. Then by starting a front-side isotropic porous Si-etching from the exposed surface of said domain for fabricating the micromechanical element and by continuing the etching until said portion that will carry the micromechanical element after its fabrication becomes at least in its full extent underetched, a porous Si sacrificial layer is created which at least partially encloses said portion that will carry the micromechanical element after its fabrication. As a next step, the exposed surface of said porous Si sacrificial layer is passivated by applying a metallic thin film thereon and metallic contact pieces of the circuit element through the known steps of CMOS technology are formed. Finally, the metallic thin film that covers the exposed surface of the porous Si sacrificial layer is removed and the micromechanical element is formed by chemically dissolving said porous Si sacrificial layer.

Claims

1-31. -31. (canceled)

32. Process for fabricating a monocrystalline silicon (Si) micromechanical element integrated with a complementary metal-oxide-semiconductor (CMOS) circuit element within the CMOS technology, comprising the processing sequence of:

(a) forming a domain of n-type semiconducting property within a monocrystalline Si substrate of p-type semiconducting property for the n-well of a CMOS circuit element;

(b) forming patterns of n-type domains within the substrate simultaneously with or immediately after step (a) for the micromechanical element;

(c) fabricating the CMOS circuit element within the substrate through the known steps of CMOS technology;

(d) covering the circuit element, as well as the patterns of said domain formed in step for the micromechanical element with a protecting layer;

(e) starting a front-side isotropic porous Si-etching from the surface of the non-protected domains of p-type semiconducting property of step (d) for fabricating the micromechanical element to become at least in its full extent underetched, thereby creating a porous Si sacrificial layer with an exposed surface which at least partially encloses said patterns after its fabrication;

(f) passivating the exposed surface of said porous Si sacrificial layer by applying a metallic thin film thereon;

(g) forming metallic contact pieces of the circuit element through the known steps of CMOS technology; and

(h) removing the metallic thin film that covers the exposed surface of the porous Si sacrificial layer and releasing the micromechanical element by chemically dissolving said porous Si sacrificial layer.

42. A tactile sensor array comprising

sensor chips fabricated on a semiconductor wafer, each sensor chip comprising CMOS circuit elements and sensing micromechanical elements in integrated form, wherein said sensing micromechanical elements are arranged in columns and rows;

CMOS decoders in a number being equal to the number of rows/columns electrically - connected to each sensing micromechanical element in a single row/column through MOS transfer gates of said CMOS circuit elements enabling simultaneous read-out of electrical signals generated by the addressed micromechanical sensing elements in a single row/column;

MOS transistors driving piezoresistive elements through said MOS transfer gates as current generators, said piezoresistive elements being provided in the micromechanical sensing elements;

Dividers for adjusting the operating points of said MOS transistors.