RECESS GATE TRANSISTOR

• US 20090261420A1
• Filed: 12/11/2008
• Published: 10/22/2009
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Bong-Su, Jang, Dae-Young, Lee, Ho-Jun, Kim, Dae-Ik, Lee, Si-Hyung, Ryu, Ho-In
• Granted Patent: US 8,889,539 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.

Claims

1. A method of forming a semiconductor device, comprising:

forming at least two trenches extending vertically from a bottom portion to an upper portion;

forming an insulating layer on the trenches including the trench walls;

forming a conductive layer on the insulating layer;

removing the conductive layer from the upper portion of the trenches, with a conductive layer pattern remaining at the bottom portion of the trenches;

depositing a buffer layer on the conductive layer patterns and the trench walls; and

filling the upper portions of the trenches with a capping layer.

2. The method of claim 1, wherein the insulating material is silicon oxide.

3. The method of claim 1, wherein the gate-to-gate dimension is 0.1 um or less.

4. The method of claim 1, wherein the conductive material is made from a metal group consisting of one of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

5. The method of claim 1, wherein the buffer layer is made of silicon oxide.

6. The method of claim 1, wherein the capping layer is made of an insulating material, from one of an oxide, nitride, SiO2, SiON, SixNy, or silicon nitride.

7. The method of claim 1, wherein the etch selectivity of the capping layer is higher than that of the buffer layer.

8. The method of claim 1, further including forming a plurality of hard masks including a polysilicon layer on the substrate.

9. A semiconductor device, comprising:

a substrate having a plurality of trenches, each of the trenches disposed between contacts formed on the top surface of an ILD layer formed on the substrate, each trench having trench walls and extending vertically from a bottom portion to an upper portion;

an insulating layer formed on the trenches including the bottom portions and the trench walls;

a conductive layer pattern formed at the bottom portion of each of the trenches;

a buffer layer formed on the conductive layer pattern and the trench walls; and

a cap formed on the buffer layer from above the conductive layer patterns to the top of the trenches.

10. The semiconductor device of claim 9, wherein the distance from trench-to-trench is 0.1 um or less.

11. The semiconductor device of claim 9, wherein the substrate is partitioned into a cell region, a core region, and a peripheral region, wherein the trenches are disposed in the cell region and not in the core region or the peripheral region.

12. The semiconductor device of claim 9, wherein the buffer layer is made of silicon oxide, and the cap is made of silicon nitride.

13. The semiconductor device of claim 12, wherein the ILD layer is made of BPSG.

14. The semiconductor device of claim 9, wherein the cap comprises more than one capping layer.

15. The semiconductor device of claim 9, wherein the conductive layer pattern comprises a first conductive layer and a second conductive layer made of different conductive materials.

16. The semiconductor device of claim 15, wherein the first conductive layer is made from a metal group consisting of one of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru, and the second conductive layer is made from polysilicon,

17. A method of forming a semiconductor device, comprising:

forming a plurality of hard masks on a substrate by patterning an insulating layer;

forming a plurality of trenches in the substrate, each trench having trench walls disposed between a pair of masks and extending vertically from a bottom portion to an upper portion;

forming an insulating layer on the trenches including the trench walls;

forming a first conductive layer on the insulating layer;

etching the first conductive layer to form first conductive layer patterns to fill the bottom portions of the trenches;

forming a second conductive layer on the first conductive layer patterns;

etching the second conductive layer to form second conductive layer patterns above the first conductive layer patterns;

depositing a buffer layer on the second conductive layer patterns and the trench walls; and

filling the upper portions of the trenches with a capping layer.

18. The method of claim 17, wherein the first conductive layer pattern is formed from a metal layer and the second conductive layer pattern is formed from a polysilicon layer.

19. The method of claim 18, wherein the trenches form part of an NMOS device and the metal layer has a workfunction equal to or greater than a workfunction of the polysilicon layer.

20. The method of claim 18, wherein the trenches form part of a PMOS device and the metal layer has a workfunction equal to or less than a workfunction of the polysilicon layer.

21. The method of claim 18, wherein the metal layer is selected from a group consisting of one of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, or Ru.

22. The method of claim 21, wherein the second conductive layer is selected from a group consisting of one of Ti, TiN, W, WN, Ta, TaN, Co, C, Rb, and Ru.

23. The method of claim 17, wherein the first insulating material is silicon nitrite and the second insulating material is silicon oxide.

24. The method of claim 17, wherein the dimension from trench to trench is 0.1 um or less.

25. The method of claim 17, wherein after the step of etching the capping layer, depositing a second capping layer on the etched capping layer to form first and second capping patterns.

26. The method of claim 17, wherein the buffer layer is made of silicon oxide and the capping layer is made of silicon nitride.

27. The method of claim 17, further including:

planarizing the hard masks and the capping layer;

depositing an interlayer dielectric (ILD) layer on the substrate; and

etching the ILD layer to form contact holes,

wherein the etch selectivity of the ILD is higher than the etch selectivity of the buffer layer.

28. The method of claim 17, wherein the etch selectivity of the capping layer is higher than that of the buffer layer.

29. The method of claim 17, wherein the step of forming a plurality of hard masks includes forming a polysilicon layer on the substrate prior to forming the first insulating layer.

30. A method of forming a semiconductor device, comprising:

forming a substrate and an active layer at a top portion of the substrate;

forming a polysilicon layer on the active layer;

forming a first insulation layer on the polysilicon layer;

forming a plurality of masks by patterning the first insulating layer and the polysilicon layer;

forming a plurality of trenches having trench walls in the substrate, each trench disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion;

forming a second insulating layer on the trench walls;

forming a conductive layer on the second insulating layer;

etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches;

depositing a buffer layer on the conductive layer patterns and the trench walls;

filling the upper portions of the trenches with a capping layer;

planarizing the capping layer, the buffer layer, and the hard masks to expose the active layer at the top portion of the substrate;

forming an ILD layer on active layer, the buffer layer, and the capping layer; and

etching the ILD layer above the active layer to form contact holes.

31. The method of claim 30, wherein the etch selectivity from the ILD layer to the capping layer is higher than the etch selectivity from the ILD layer to the buffer layer.

32. A semiconductor memory card, comprising:

a memory controller and a memory device, the memory controller controls the memory device to read or write data from/into the memory in response to a read/write request of a host, wherein the memory device comprises;

a substrate having a plurality of trenches, each of the trenches disposed between contacts formed on the top surface of an ILD layer formed on the substrate, each trench having trench walls and extending vertically from a bottom portion to an upper portion;

an insulating layer formed on the trenches including the bottom portions and the trench walls;

a conductive layer pattern formed at the bottom portion of each of the trenches;

a buffer layer formed on the conductive layer pattern and the trench walls; and

a cap formed on the buffer layer from above the conductive layer patterns to the top of the trenches.

33. The semiconductor memory card of claim 32, wherein the distance from trench-to-trench of the memory device is 0.1 um or less.

34. The semiconductor memory card of claim 32, wherein the host is a mobile device or a processing device having a processor.

35. The semiconductor memory card of claim 32, further including a wireless interface for communicating with another cellular device.

36. The semiconductor memory card of claim 32, further including a connector for removably connecting to a host system, wherein the host system is one of a personal computer, notebook computer, hand held computing device, camera, or audio reproducing device.

37. An electronic device comprising:

a controller having a processor;

an input/output (I/O) device;

a memory device; and

a wireless interface, wherein the I/O device includes a display, wherein the wireless interface transmits or receives data via a wireless communication network, and wherein the memory device comprises;

a substrate having a plurality of trenches, each of the trenches disposed between contacts formed on the top surface of an ILD layer formed on the substrate, each trench having trench walls and extending vertically from a bottom portion to an upper portion;

an insulating layer formed on the trenches including the bottom portions and the trench walls;

a conductive layer pattern formed at the bottom portion of each of the trenches;

a buffer layer formed on the conductive layer pattern and the trench walls; and

a cap formed on the buffer layer from above the conductive layer patterns to the top of the trenches.

38. The electronic device of claim 37, wherein the wireless communication network communicates in a communication interface protocol of a third generation communication system, including one of code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), extended-time division multiple access (E-TDMA), wide band code division multiple access (WCDMA), or CDMA2000.