SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE

• US 20090261421A1
• Filed: 10/21/2008
• Published: 10/22/2009
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: HVVi Semiconductors Incorporated
• Inventors: Gogoi, Bishnu Prasanna
• Granted Patent: US 7,919,801 B2
• Time in Patent Office: Days
• US Class Current: 257/378
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Claims

1. A method of forming a semiconductor structure, the method comprising:

forming a first opening in a semiconductor material;

forming a dielectric material in the first opening;

forming a unidirectional transistor, wherein forming the unidirectional transistor comprises forming a shield layer over the semiconductor material and forming a control electrode of the unidirectional transistor over the semiconductor material after forming the shield layer, wherein at least a portion of the shield layer is disposed between at least a portion of the control electrode and at least a portion of the semiconductor material; and

simultaneously forming a first portion of the unidirectional transistor and a first portion of a bidirectional transistor in or over the semiconductor material, wherein the dielectric material is between a second portion of the unidirectional transistor and a second portion of the bidirectional transistor.

2. The method of claim 1, further comprising providing a semiconductor substrate, wherein the semiconductor substrate comprises the semiconductor material, wherein the semiconductor material comprises silicon, and wherein forming a dielectric material in the first opening comprises performing a thermal oxidation to convert a portion of the silicon to silicon dioxide.

3. The method of claim 1, wherein forming the control electrode of the unidirectional transistor comprises forming a gate electrode of the unidirectional transistor and further comprising forming a gate electrode of the bidirectional transistor, wherein the first portion of the unidirectional transistor is the gate electrode of the unidirectional transistor and the first portion of the bidirectional transistor is the gate electrode of the bidirectional transistor, and wherein a gate length of the unidirectional transistor is less than a gate length of the bidirectional transistor.

4. The method of claim 1, further comprising forming the first portion of the unidirectional transistor after the forming of the dielectric material, wherein forming the first opening comprises forming the first opening to extend from a surface of the semiconductor material to a distance of at least about one micron or greater below the surface of the semiconductor material, wherein a breakdown voltage of the unidirectional transistor is at least about ten volts or greater and a breakdown voltage of the bidirectional transistor is about six volts or less.

5. The method of claim 1, wherein forming a first portion of the unidirectional transistor comprises forming a doped region in the semiconductor material and further comprising forming a dielectric structure below the surface of the semiconductor material, wherein forming the dielectric structure comprises forming the first opening and forming the dielectric material, wherein the dielectric structure extends to a distance below the lower boundary of the doped region and the dielectric structure surrounds the doped region, and wherein a dielectric constant of the dielectric structure is about 3.9 or lower.

6. The method of claim 1, wherein the unidirectional transistor is a field effect transistor (FET) having a gate, a source region, a drain region, and a channel region between the source region and drain region and under the gate and wherein forming the unidirectional transistor comprises forming the gate after forming the channel region.

7. A semiconductor structure, comprising:

a semiconductor material having a first opening formed therein;

a dielectric material disposed in the first opening;

a unidirectional transistor, wherein the unidirectional transistor comprises a shield layer over the semiconductor material and a control electrode of the unidirectional transistor disposed over the semiconductor material, wherein at least a portion of the shield layer is disposed between at least a portion of the control electrode and at least a portion of the semiconductor material; and

a first portion of the unidirectional transistor and a first portion of a bidirectional transistor being disposed in or over the semiconductor material, wherein the dielectric material is between a second portion of the unidirectional transistor and a second portion of the bidirectional transistor.

8. A semiconductor structure of claim 7, further comprising a semiconductor substrate, wherein the semiconductor substrate comprises the semiconductor material, wherein the semiconductor material comprises silicon, and wherein the dielectric material disposed in the first opening comprises a converted portion of the silicon to silicon dioxide via thermal oxidation.

9. A semiconductor structure of claim 7, wherein the control electrode of the unidirectional transistor comprises a gate electrode of the unidirectional transistor and further comprising a gate electrode of the bidirectional transistor, wherein the first portion of the unidirectional transistor is the gate electrode of the unidirectional transistor and the first portion of the bidirectional transistor is the gate electrode of the bidirectional transistor, and wherein a gate length of the unidirectional transistor is less than a gate length of the bidirectional transistor.

10. A semiconductor structure of claim 7, wherein the first opening extends from a surface of the semiconductor material to a distance of at least about one micron or greater below the surface of the semiconductor material, wherein a breakdown voltage of the unidirectional transistor is at least about ten volts or greater and a breakdown voltage of the bidirectional transistor is about six volts or less.

11. A semiconductor structure of claim 7, wherein a first portion of the unidirectional transistor comprises a doped region in the semiconductor material and further comprising a dielectric structure disposed at least partially below the surface of the semiconductor material, wherein the dielectric structure extends to a distance below a lower boundary of the doped region and the dielectric structure surrounds the doped region, and wherein a dielectric constant of the dielectric structure is about 3.9 or lower.

12. A semiconductor structure of claim 7, wherein the unidirectional transistor comprises a field effect transistor (FET) having a gate, a source region, a drain region, and a channel region disposed between the source region and drain region and under the gate.