LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE

• US 20090261426A1
• Filed: 04/17/2008
• Published: 10/22/2009
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Zierak, Michael J., Voldman, Steven H., Feilchenfeld, Natalie B., Gambino, Jeffrey P., Voegeli, Benjamin T., Liu, Xuefeng
• Granted Patent: US 8,114,750 B2
• Time in Patent Office: Days
• US Class Current: 257/408
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.

Claims

1. A method manufacturing a semiconductor structure comprising:

forming a gate dielectric and a gate electrode on a semiconductor substrate;

forming a first gate spacer directly on said gate electrode;

forming a second gate spacer directly on said first gate spacer;

removing a first portion of said second gate spacer on a source side of said gate electrode;

forming a source region in said semiconductor substrate on said source side of said gate electrode after removal of said first portion of said second gate spacer;

forming a drain region in said semiconductor substrate on a drain side of said gate electrode; and

removing a second portion of said second gate spacer on said drain side of said gate electrode after formation of said drain region.

2. The method of claim 1, wherein an edge of said source region is substantially coincident with an outer sidewall of said first gate spacer.

3. The method of claim 1, wherein an edge of said drain region is substantially coincident with a first outer sidewall of said second gate spacer.

4. The method of claim 1, further comprising forming a dielectric cap directly on said gate electrode, wherein said dielectric cap and said gate electrode have vertically coincident sidewalls.

5. The method of claim 4, wherein said second gate spacer is formed on directly on said dielectric cap, and wherein said dielectric cap comprises borophosphosilicate glass (BPSG).

6. The method of claim 1, wherein said second gate spacer comprises a material selected from germanium, a silicon germanium alloy containing germanium at an atomic concentration of 25% or greater, an anti-reflective coating material, and silicon oxide containing hydrogen at an atomic concentration of 1.0% or greater.

7. The method of claim 1, further comprising:

forming a first conductivity type well having a doping of a first conductivity type underneath a source side edge of said gate electrode in said semiconductor substrate, wherein said first conductivity type well abuts said gate dielectric, wherein said source region is formed in said first conductivity type well and has a doping of said second conductivity type; and

forming a drift region having a doping of a second conductivity type underneath a drain side edge of said gate electrode in said semiconductor substrate, wherein said drift region abuts said gate dielectric, wherein said second conductivity type is the opposite of said first conductivity type, and wherein said drain region is formed within said drift region and has a doping of said second conductivity type.

8. The method of claim 7, further comprising forming a substrate contact semiconductor region having a doping of said first conductivity type in said semiconductor substrate, wherein an edge of said substrate contact semiconductor region is substantially coincident with a second outer sidewall of said second gate spacer.

9. The method of claim 7, wherein a first lateral distance between said substrate contact semiconductor region and said gate electrode is the same as a second lateral distance between said drain region and said gate electrode.

10. A method manufacturing a semiconductor structure comprising:

forming a gate dielectric and a gate electrode material layer on a semiconductor substrate;

forming a gate electrode and a disposable conductive portion disjoined from said gate electrode by patterning said gate electrode material layer;

forming a dielectric gate spacer directly on sidewalls of said gate electrode and said disposable conductive portion, wherein said dielectric gate spacer contains two holes laterally enclosing said gate electrode and said disposable conductive portion; and

forming a source region and a drain region in said semiconductor substrate, wherein an edge of said source region is substantially vertically coincident with an outer sidewall of a first portion of said dielectric gate spacer laterally abutting said gate electrode, and wherein an edge of said drain region is substantially vertically coincident with an outer sidewall of a second portion of said dielectric gate spacer laterally abutting said disposable conductive portion.

11. The method of claim 10, wherein said dielectric gate spacer is of unitary construction and comprises said first portion, said second portion, and a third portion, wherein said first portion laterally abuts said gate electrode and does not abut said disposable conductive portion, said second portion laterally abuts said disposable conductive portion and does not abut said gate electrode, and a third portion laterally abuts said gate electrode and said disposable conductive portion.

12. The method of claim 10, wherein a lateral distance between said gate electrode and said disposable conductive portion is less than twice a lateral width of said first portion as measured at a bottom of said first portion.

13. The method of claim 10, further comprising:

lithographically masking said gate electrode with a photoresist, while exposing said disposable conductive portion; and

removing said disposable conductive portion, while preserving said gate electrode.

14. The method of claim 13, further comprising forming a drift region underneath an opening formed by removal of said disposable conductive portion by implanting dopant ions into said opening.

15. The method of claim 14, further comprising forming a first conductivity type well having a doping of a first conductivity type underneath a source side edge of said gate electrode in said semiconductor substrate, wherein said first conductivity type well abuts said gate dielectric, wherein said source region is formed in said first conductivity type well and has a doping of said second conductivity type, wherein said drift region has a doping of a second conductivity type which is the opposite of said first conductivity type, wherein said drift region laterally abuts said drain region, and wherein said source region and said drain region have a doping of said second conductivity type.

16. The method of claim 15, further comprising forming a substrate contact semiconductor region having a doping of said first conductivity type in said semiconductor substrate, wherein said substrate contact semiconductor region laterally abuts said source region.

17. A semiconductor structure comprising:

a first conductivity type well having a doping of a first conductivity type and located in a semiconductor substrate;

a drift region having a doping of a second conductivity type which is the opposite of said first conductivity type, and located in said semiconductor substrate;

a gate dielectric vertically abutting said first conductivity type well and said drift region;

a gate electrode vertically abutting said gate dielectric and straddling over said first conductivity type well and said drift region; and

a dielectric gate spacer of unitary construction and including two holes, wherein a first hole is filled by said gate electrode, and wherein a second hole is filled with a dielectric material.

18. The semiconductor structure of claim 17, further comprising:

a source region having a doping of said second conductivity type and located in said first conductivity type well;

a drain region having a doping of said second conductivity type, laterally abutting said drift region, and located in said semiconductor substrate;

19. The semiconductor structure of claim 18, wherein an edge of said source region is substantially vertically coincident with a first outer sidewall of said dielectric gate spacer overlying said first conductivity type well, and wherein an edge of said drain region is substantially vertically coincident with a second outer sidewall of said dielectric gate spacer overlying said drift region.

20. The semiconductor structure of claim 19, further comprising:

a substrate contact semiconductor region having a doping of said first conductivity type and located in said semiconductor substrate, wherein said substrate contact semiconductor region laterally abuts said source region; and

a substrate layer having a doping of said first conductivity type, abutting said first conductivity type well and said drift region, located in said semiconductor substrate, and having a lower doping concentration than said first conductivity type well.