One-Mask MTJ Integration for STT MRAM

• US 20090261433A1
• Filed: 01/19/2009
• Published: 10/22/2009
• Est. Priority Date: 04/21/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kang, Seung H., Lee, Kangho, Bang, David
• Granted Patent: US 9,159,910 B2
• Time in Patent Office: Days
• US Class Current: 257/421
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10B 61/00 Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit includes providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect. Over the first interlevel dielectric layer and the first metal interconnect, magnetic tunnel junction material layers are deposited. From the material layers a magnetic tunnel junction stack, coupled to the first metal interconnect, is defined using a single mask process. The magnetic tunnel junction stack is integrated into the integrated circuit.

Claims

1. A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit comprising:

providing in a semiconductor back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect;

depositing over the first interlevel dielectric layer and the first metal interconnect a plurality of magnetic tunnel junction material layers; and

defining from the plurality of material layers a magnetic tunnel junction stack coupled to the first metal interconnect using a single mask process, the magnetic tunnel junction stack being integrated into the integrated circuit.

2. The method of claim 1, further comprising continuing the BEOL process flow to provide a second metal interconnect in communication with the magnetic tunnel junction stack.

3. The method of claim 1, in which depositing the plurality of magnetic tunnel junction material layers comprises:

depositing a first electrode layer;

depositing a plurality of magnetic tunnel junction layers on the first electrode layer; and

depositing a second electrode layer on the plurality of magnetic tunnel junction layers.

4. The method of claim 3, wherein the depositing a plurality of magnetic tunnel junction layers comprises:

depositing a fixed polarization magnetization layer;

depositing a tunnel barrier layer; and

depositing a free polarization magnetization layer.

5. The method of claim 1, further comprising:

depositing a first dielectric passivation barrier layer over the magnetic tunnel junction stack and the substrate;

depositing a second interlevel dielectric layer on the first dielectric passivation barrier layer; and

planarizing the second interlevel dielectric layer and the first dielectric passivation barrier layer to expose an electrode of the defined MTJ stack.

6. The method of claim 5, further comprising:

forming a second dielectric passivation barrier layer on the second interlevel dielectric layer and the exposed electrode;

forming a third interlevel dielectric layer on the second dielectric passivation barrier layer; and

forming a second metal interconnect in the third interlevel dielectric layer and the second dielectric passivation barrier, the second metal interconnect being in communication with the electrode.

7. The method of claim 1, further comprising forming a third metal interconnect in the first interlevel dielectric layer positioned apart from the magnetic tunnel junction stack, the third metal interconnect being formed before depositing the plurality of MTJ material layers.

8. The method of claim 7, further comprising:

depositing a first dielectric passivation barrier layer on the magnetic tunnel junction stack and the substrate;

depositing a second interlevel dielectric layer on the first dielectric passivation barrier layer;

forming a conductive via in the second interlevel dielectric and the first dielectric passivation barrier layer positioned to communicate with the third metal interconnect;

depositing a second dielectric passivation barrier layer on the second interlevel dielectric layer and the conductive via;

depositing a third interlevel dielectric on the second dielectric passivation barrier layer; and

forming a fourth metal interconnect in the third interlevel dielectric layer and the second dielectric passivation barrier layer, the fourth metal interconnect communicating with the conductive via.

9. The method of claim 8, wherein the conductive via is formed after the depositing of the second interlevel dielectric layer and before the depositing of the second dielectric passivation barrier layer, and the fourth metal interconnect is formed after the depositing of the second dielectric passivation barrier layer and the third interlevel dielectric layer in a single damascene process.

10. The method of claim 8, wherein the conductive via and the fourth metal interconnect are formed after the depositing of the third interlevel dielectric layer and the second dielectric passivation barrier layer in a dual damascene process.

11. The method of claim 1, wherein the integrated circuit is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated.

12. A magnetic tunnel junction device in an integrated circuit (IC) including at least a magnetic random access memory (MRAM) comprising:

a substrate comprising a first metal interconnect;

a magnetic tunnel junction stack communicating with the first metal interconnect, the magnetic tunnel junction stack having been defined using a single mask process; and

a second metal interconnect in communication with the magnetic tunnel junction stack,

wherein the magnetic tunnel device is integrated into the IC.

13. The MTJ device of claim 12, wherein the magnetic tunnel junction stack comprises:

a first electrode;

a plurality of magnetic tunnel junction layers, at least one of the magnetic tunnel junction layers being on the first electrode layer; and

a second electrode on at least one of the magnetic tunnel junction layers.

14. The MTJ device of claim 13, wherein the magnetic tunnel junction layers comprise:

a fixed polarization magnetization layer;

a tunnel barrier layer; and

a free polarization magnetization layer.

15. The MTJ device of claim 13, further comprising:

a first interlevel dielectric layer in the substrate;

a first dielectric passivation barrier layer on the magnetic tunnel junction stack and the substrate; and

a second interlevel dielectric layer on the first dielectric passivation barrier layer, the second interlevel dielectric layer and the first dielectric passivation barrier layer exposing the second electrode of the magnetic tunnel junction stack.

16. The MTJ device of claim 15 further comprising:

a second dielectric passivation barrier layer on the second interlevel dielectric layer and the second electrode;

a third interlevel dielectric layer on the second dielectric passivation barrier layer; and

a second metal interconnect in the third interlevel dielectric layer and the second dielectric passivation barrier, the second metal interconnect being in communication with the second electrode.

17. The MTJ device of claim 16 further comprising:

a third metal interconnect in the first interlevel dielectric;

a conductive via in the second interlevel dielectric and the first dielectric passivation barrier layer, the conductive via being in communication with the third metal interconnect; and

a fourth metal interconnect in the third interlevel dielectric layer and the second dielectric passivation barrier layer, the fourth metal interconnect being in communication with the conductive via.

18. The MTJ device of claim 12, further comprising a barrier layer between a first interlevel dielectric of the substrate and the magnetic tunnel junction stack.

19. The MTJ device of claim 12, wherein the MTJ device is incorporated in a device selected from the group consisting of a mobile phone, personal data assistant (PDA), navigation device, fixed location data unit, set-top box, music player, video player, entertainment unit, and computer.

20. A method for integrating a magnetic tunnel junction (MTJ) device into an integrated circuit comprising the steps of:

providing in a back-end-of-line (BEOL) process flow a substrate having a first interlevel dielectric layer and at least a first metal interconnect;

depositing over the first interlevel dielectric layer and the first metal interconnect a plurality of magnetic tunnel junction material layers; and

defining from the plurality of material layers a magnetic tunnel junction stack coupled to the first metal interconnect using a single mask process, the magnetic tunnel junction stack being integrated into the integrated circuit.

21. The method of claim 20, wherein the integrated circuit is applied in an electronic device, selected from a group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated.

22. A magnetic tunnel junction (MTJ) structure for magnetic random access memory (MRAM) comprising:

a first interconnect means for communicating with at least one control device;

a first electrode means for coupling to the first interconnect means;

an MTJ means for storing data, the MTJ means coupling to the first electrode means;

a second electrode means for coupling to the MTJ means, the first and second electrode means having a same lateral dimension as the MTJ means based upon a first mask; and

a second interconnect means for coupling to the second electrode means and at least one other control device.

23. The MTJ structure of claim 22, integrated into a spin-torque-transfer (STT) MRAM.

24. The MTJ structure of claim 23, in which the STT MRAM is coupled to a microprocessor.

25. The MTJ structure of claim 23, in which the STT MRAM is integrated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, microprocessor, and a computer.