Two Mask MTJ Integration For STT MRAM

• US 20090261437A1
• Filed: 03/17/2009
• Published: 10/22/2009
• Est. Priority Date: 04/18/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Kang, Seung H., Nowak, Matthew, Li, Xia, Gu, Shiqun
• Granted Patent: US 8,125,040 B2
• Time in Patent Office: Days
• US Class Current: 257/422
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.

Claims

1. A method for forming a magnetic tunnel junction (MTJ) device for magnetic random access memory (MRAM) using two masks comprising:

depositing, on a substrate comprising a first interconnect metallization, a first electrode in communication with the first interconnect metallization, MTJ layers, and a second electrode;

defining at least at least one of the MTJ layers and the second electrode with a first mask;

depositing a third electrode on the second electrode; and

defining the first electrode and the third electrode with a second mask larger than the first mask.

2. The method of claim 1, in which the defining at least some of the MTJ layers comprises defining a tunnel barrier layer and a free layer with the first mask;

and

defining the first electrode and second electrode further comprises defining a reference fixed magnetic layer stack with the second mask.

3. The method of claim 1, in which the defining at least some of the MTJ layers comprises defining a tunnel barrier layer, a free layer, and a reference fixed magnetic layer stack with the first mask.

4. The method of claim 1, further comprising:

depositing a first dielectric passivation barrier over the defined MTJ layers and the defined second contact prior to depositing the third electrode; and

planarizing the first dielectric passivation barrier to expose the second electrode of the defined MTJ stack prior to depositing the third electrode.

5. The method of claim 4, further comprising

depositing a second dielectric passivation barrier on the defined contacts and the substrate;

depositing an interlevel dielectric layer on the second dielectric passivation barrier; and

forming a second interconnect metallization in at least the second dielectric passivation barrier, the second metal interconnect being in communication with the third electrode.

6. A magnetic tunnel junction (MTJ) structure for magnetic random access memory (MRAM) comprising:

a substrate comprising a first interconnect metallization;

a first electrode coupled to the first interconnect metallization;

a plurality of MTJ layers, at least one of the MTJ layers being coupled to the first electrode;

a second electrode coupled to at least one other of the MTJ layers, the second electrode having a same lateral dimension as at least some of the MTJ layers based upon a first mask;

a third electrode coupled to the second electrode, the third electrode having a same lateral dimension as the first electrode based upon a second mask; and

a second interconnect metallization coupled to the third electrode.

7. The MTJ structure of claim 6, further comprising

a first dielectric passivation barrier on the MTJ layers and second electrode.

8. The MTJ structure of claim 7, in which the at least some MTJ layers comprise a fixed magnetization layer, an insulating tunnel barrier layer, and a ferromagnetic free layer.

9. The MTJ structure of claim 7, in which the at least some MTJ layers comprise an insulating tunnel barrier layer, and a ferromagnetic free layer.

10. The MTJ structure of claim 7, in which the first electrode is tantalum.

11. The MTJ structure of claim 7, further comprising a second dielectric passivation layer deposited over the first electrode, the third electrode, and the substrate.

12. The MTJ structure of claim 11, in which the substrate further comprises a first interlevel dielectric layer.

13. The MTJ structure of claim 8, in which the fixed magnetization layer comprises a synthetic antiferromagnetic layer and an antiferromagnetic layer.

14. The MTJ structure of claim 7, integrated into a spin-torque-transfer (STT) MRAM.

15. The MTJ structure of claim 14, in which the STT MRAM is integrated into at least one semiconductor die.

16. The MTJ structure of claim 14, in which the STT MRAM is integrated into a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, a microprocessor, and a computer.

17. A method for forming a magnetic tunnel junction (MTJ) device for magnetic random access memory (MRAM) using two masks comprising the steps of:

depositing, on a substrate comprising a first interconnect metallization, a first electrode in communication with the first interconnect metallization, MTJ layers, and a second electrode;

defining at least some of the MTJ layers and the second electrode with a first mask;

depositing a third electrode on the second electrode; and

defining the first electrode and the third electrode with a second mask larger than the first mask.

18. A magnetic tunnel junction (MTJ) structure for magnetic random access memory (MRAM) comprising:

a first interconnect means for communicating with at least one control device;

a first electrode means for coupling to the first interconnect means;

an MTJ means for storing data, the MTJ means coupling to the first electrode means;

a second electrode means for coupling to the MTJ means, the second electrode means having a same lateral dimension as the MTJ means based upon a first mask;

a third electrode means for coupling to the second electrode means, the third electrode means having a same lateral dimension as the first electrode means based upon a second mask; and

a second interconnect means for coupling to the third electrode means and at least one other control device.

19. The MTJ structure of claim 18, integrated into a spin-torque-transfer (STT) MRAM.

20. The MTJ structure of claim 19, in which the STT MRAM is integrated into at least one semiconductor die.

21. The MTJ structure of claim 19, in which the STT MRAM and microprocessor are integrated into a device selected from the group consisting of a settop box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer.