SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE

• US 20090261446A1
• Filed: 10/21/2008
• Published: 10/22/2009
• Est. Priority Date: 10/26/2007
• Status: Active Grant

• Current Assignee: Xenogenic Development Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Estivation Properties LLC (Intellectual Ventures LLC)
• Inventors: Gogoi, Bishnu P.
• Granted Patent: US 8,125,044 B2
• Time in Patent Office: Days
• US Class Current: 257/500
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/76208 using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/66719 : With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7816 : Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

In various embodiments, semiconductor structures and methods to manufacture these structures are disclosed. In one embodiment, a method includes forming a portion of the unidirectional transistor and a portion of a bidirectional transistor in or over a semiconductor material simultaneously. Other embodiments are described and claimed.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming at least one recess in a semiconductor layer;

forming a unidirectional device in and over a first region of the semiconductor layer comprising the at least one recess; and

forming a bidirectional device in and over a second region of the semiconductor layer.

2. The method of claim 1, wherein:

forming the unidirectional device and forming the bidirectional device comprise;

simultaneously forming at least a portion of the unidirectional device and at least a portion of the bidirectional device.

3. The method of claim 1, wherein the second region of the semiconductor layer is substantially devoid of the recess.

4. The method of claim 1, further comprising:

providing a semiconductor substrate, wherein the semiconductor substrate comprises the semiconductor layer;

wherein said forming the unidirectional device further comprises forming at least a portion of a higher voltage device in the at least one recess; and

wherein said forming the bidirectional device further comprises forming at least a portion of a lower voltage device in the second region.

5. A semiconductor device, comprising:

a semiconductor layer having at least one recess formed therein;

a unidirectional device disposed in and over a first region of the semiconductor layer comprising the at least one recess; and

a bidirectional device disposed in and over a second region of the semiconductor layer.

6. The semiconductor device of claim 5, wherein:

at least a portion of the unidirectional device and at least a portion of the bidirectional device are formed simultaneously or nearly simultaneously.

7. The semiconductor device of claim 5, wherein the second region of the semiconductor layer is substantially devoid of the recess.

8. The semiconductor device of claim 5, further comprising:

a semiconductor substrate, wherein the semiconductor substrate comprises the semiconductor layer;

wherein the unidirectional device further comprises at least a portion of a higher voltage device disposed in the at least one recess; and

wherein the bidirectional device further comprises at least a portion of a lower voltage device disposed in the second region.

9. A method of forming a semiconductor structure, the method comprising:

forming a first dielectric structure extending from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate;

forming a second dielectric structure extending form the second surface of the semiconductor structure and contacting the first dielectric structure; and

forming a portion of an active device in the semiconductor substrate and adjacent to the first dielectric structure.

10. The method of claim 9, wherein forming the first dielectric structure comprises:

forming a first trench in the semiconductor substrate extending from the first surface into the semiconductor substrate; and

forming silicon dioxide along a sidewall of the first trench using a thermal oxidation; and

wherein forming the second dielectric structure comprises;

forming a second trench extending from the second surface of the semiconductor substrate to the silicon dioxide of the first dielectric structure; and

depositing an oxide in the second trench contacting the silicon dioxide.

11. A semiconductor structure, comprising:

a first dielectric structure extending from a first surface of a semiconductor substrate toward a second surface of the semiconductor substrate;

a second dielectric structure extending form the second surface of the semiconductor structure and contacting the first dielectric structure; and

an active device, wherein at least a portion of the active device is disposed in the semiconductor substrate and adjacent to the first dielectric structure.

12. The semiconductor structure of claim 13, wherein:

the first dielectric structure comprises;

a first portion of the semiconductor substrate having a first trench formed therein extending from the first surface into the semiconductor substrate; and

silicon dioxide disposed along a sidewall of the first trench via thermal oxidation; and

wherein the second dielectric structure comprises;

a second portion of the semiconductor substrate having a second trench formed therein extending from the second surface of the semiconductor substrate to the silicon dioxide of the first dielectric structure; and

an oxide deposited in the second trench at least partially contacting the silicon dioxide.