DIE STACKING WITH AN ANNULAR VIA HAVING A RECESSED SOCKET

• US 20090261457A1
• Filed: 04/22/2008
• Published: 10/22/2009
• Est. Priority Date: 04/22/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pratt, Dave
• Granted Patent: US 7,821,107 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16147 the bump connector connecting to a bonding area disposed in a recess of the surface
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/81141 Guiding structures both on and outside the body
• CPC Class Codes: H01L 2224/81191 wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A die stack including a die having an annular via with a recessed conductive socket and methods of forming the die stack provide a structure for use in a variety of electronic systems. In an embodiment, a die stack includes a conductive pillar on the top of a die inserted into the recessed conductive socket of another die.

Claims

1. An apparatus comprising:

a substrate including a conductive annular via having a recessed portion surrounded by inner walls of the annular via on a bottom surface of the substrate;

a conductive layer covering the recessed portion configured as a conductive socket.

2. The apparatus of claim 1, wherein the substrate includes silicon, the conductive annular via includes copper, and the conductive layer includes under bump material.

3. The apparatus of claim 1, wherein the annular via includes a planar end portion covering a portion of a top surface of the substrate.

4. The apparatus of claim 3, further including a conductive cylindrical pillar extending out from the planar end portion of the annular via.

5. The apparatus of claim 4, wherein the conductive cylindrical pillar is vertical with respect to a plane of the substrate.

6. The apparatus of claim 1, wherein the substrate is a part of a die and the top surface of the substrate is an active surface of the die.

7. The apparatus of claim 6, wherein the active surface of the die includes integrated electronic devices.

8. A method comprising:

forming a conductive annular via having a recessed portion surrounded by inner walls of the annular via on a bottom surface of a substrate; and

forming a conductive layer covering the recessed portion to form a conductive socket.

9. The method of claim 8, wherein the forming of the conductive annular via includes forming a planar end portion covering a portion of a top surface of the substrate.

10. The method of claim 9, further including forming a conductive cylindrical pillar on the planar end portion of the annular via extending out from the substrate.

11. An electronic package comprising:

a first die including;

a substrate having an annular through substrate via (TSV) including a planar end portion covering a portion of a first surface of the substrate;

a nonconductive layer covering portions of a second surface of the substrate surrounding the annular TSV; and

an under bump layer disposed in a recessed portion in the annular TSV at the second surface, the under bump layer configured as a conductive socket on a bottom surface of the first die, wherein the bottom surface of the first die is the second surface of the substrate; and

a second die arranged relative to the first die in the electronic package, the second die having a conductive cylindrical pillar formed on a top surface of the second die, wherein the conductive cylindrical pillar is sized to fit into the conductive socket of the first die.

12. The electronic package of claim 11, further including a conductive pad disposed between the substrate and the planar end portion of the annular TSV.

13. The electronic package of claim 11, wherein the substrate includes silicon.

14. The electronic package of claim 11, wherein at least one of the first die or the second die includes integrated electronic devices.

15. The electronic package of claim 11, wherein the annular TSV includes copper.

16. The electronic package of claim 11, wherein the nonconductive layer includes a backside passivation layer.

17. The electronic package of claim 11, wherein the first and the second die are stacked so that the conductive cylindrical pillar of the second die is fitted into the conductive socket of the first die forming a conductive connection between the conductive cylindrical pillar of the second die and the conductive socket of the first die.

18. The electronic package of claim 17, further including a top die, wherein the top die includes a metal pillar sized to fit into a conductive socket in an annular via of the second die such that the metal pillar is disposed into the conductive socket of the second die to form a conductive connection between the metal pillar and the conductive socket of the second die.

19. The electronic package of claim 17, the electronic package includes one or more additional dies connected to the stack by a conductive cylindrical pillar of one of the additional dies disposed in a conductive socket in an annular via of as the second die.

20. A method for fabricating an electronic package comprising:

configuring a first die including;

forming an annular through-substrate via (TSV) with a planar end portion covering a portion of a first surface of a substrate and with portions of the annular TSV exposed at a second surface of the substrate;

forming a nonconductive layer covering portions of the second surface of the substrate surrounding the annular TSV and leaving a recessed portion inside the annular TSV at the second surface uncovered; and

depositing an under bump layer on the recessed portion forming a conductive socket on a bottom surface of the first die, the bottom surface of the first die being the second surface of the substrate; and

configuring a second die in the electronic package relative to the first die including forming a conductive cylindrical pillar on a top surface of the second die such that the conductive cylindrical pillar is sized to fit into the conductive socket of the first die.

21. The method of claim 20, further including configuring the first die and the second die in a stack so that the conductive cylindrical pillar of the second die is fitted into the conductive socket of the first die to form a conductive connection between the conductive cylindrical pillar of the second die and the conductive socket of the first die.

22. The method of claim 21, further including disposing a top die over the stack of the first die and the second die such that a metal pillar of the top die is disposed in a conductive socket in an annular via of the second die to form a conductive connection between the metal pillar and the conductive socket of the second die.

23. The method of claim 21, wherein the method includes connecting one or more additional dies to the stack by disposing a conductive cylindrical pillar of one of the additional dies in a conductive socket in an annular via of the second die.

24. A method for fabricating an electronic package, the method comprising:

etching a substrate from a first surface of the substrate to form an annular opening;

forming a first passivation layer over sidewalls of the annular opening;

filling the annular opening with a first conductive material such that a metal via is formed, the metal via including a planar end portion covering a portion of the first surface of the substrate and extending on the first surface outward from outer edges of the annular opening;

thinning the substrate by removing a substrate material from a second surface of the substrate including an area surrounded by the metal via to an extent that a portion of the metal via extends out from the second surface of the thinned substrate;

removing the first passivation layer from inner walls and an inner portion of exposed ends of the metal via at the second surface of the thinned substrate;

forming a second passivation layer over a portion of the second surface of the substrate surrounding the inner portion of the exposed ends of the metal via such that a recessed area surrounded by inner walls of the metal via is formed; and

coating a layer of a second conductive material on the recessed area to form a conductive socket.

25. The method of claim 24, further including forming a conductive cylindrical pillar vertically extending out from the first surface of the substrate and being sized to fit into the conductive socket.

26. The method of claim 25, wherein the forming of the conductive cylindrical pillar includes forming the pillar on the planar end portion of the metal via.

27. The method of claim 24, wherein etching of the substrate is performed over an area of the first surface of the substrate coated with a conductive pad, wherein the annular opening is concentric with the conductive pad.

28. The method of claim 24, wherein forming the first passivation layer over sidewalls of the annular opening includes forming the first passivation layer over entire surfaces of the annular opening and then removing the first passivation layer from a bottom surface of the annular opening.

29. The method of claim 24, wherein the first conductive material includes copper, the second conductive material includes an under bump material, and the substrate material includes silicon.

30. A system comprising:

a processor including an electronic package formed by stacking a plurality of dies, wherein at least one die of the plurality of dies includes a recessed conductive socket formed on an annular via; and

a memory including at least one random access memory package.

31. The system of claim 30, wherein at least one die of the plurality of dies includes a conductive cylindrical pillar sized to fit into the recessed conductive socket.

32. The system of claim 30, wherein the at least one random access memory package is formed by stacking a plurality of dies, wherein at least one die of the plurality of dies includes a recessed conductive socket formed on an annular via.

33. The system of claim 33, wherein at least one die of the plurality of dies includes a conductive cylindrical pillar sized to fit into the recessed conductive socket.