Semiconductor device and manufacturing method thereof

• US 20090261476A1
• Filed: 04/18/2008
• Published: 10/22/2009
• Est. Priority Date: 04/18/2007
• Status: Abandoned Application

• Current Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Original Assignee: Siliconware Precision Industries Co., Ltd. (ASE Technology Holding Co., Ltd.)
• Inventors: Ke, Chun-Chi, Huang, Chih-Ming, Huang, Chien-Ping, Hsiao, Cheng-Hsu, Chang, Chin-Huang
• Application Number:
  US12/148,319
• Publication Number:
  US 20090261476A1
• Time in Patent Office: Days
• US Class Current: 257/766
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/82001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor device and a manufacturing method thereof are disclosed. The method includes the steps of providing a carrier board having conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads disposed thereon, wherein conductive bumps are disposed on the solder pads; mounting chips on the carrier board; filling the spacing between the chips with a dielectric layer and forming openings in the dielectric layer at periphery of each chip to expose the conductive circuits; forming a metal layer in the openings of the dielectric layer and at periphery of the active surface of the chips for electrically connecting the conductive bumps and the conductive circuits; and cutting along the dielectric layer between the chips and removing the carrier board to separate each chip and exposing the conductive circuits from the non-active surface.

Claims

1. A manufacturing method of a semiconductor device, comprising the steps of:

providing a carrier board having a plurality of conductive circuits disposed thereon and a plurality of chips with active surfaces having solder pads thereon, wherein conductive bumps are disposed on the solder pads;

mounting the chips on the carrier board, wherein the chips are spaced away from each other and cover one end of each of the conductive circuits, so as to expose the conductive circuits from spacing between the chips;

filling the spacing between the chips with a dielectric layer, and forming a plurality of openings in the dielectric layer at periphery of the chips so as to expose a part of the conductive circuits;

forming a resist layer covering surfaces of the chips and the dielectric layer, and forming openings in the resist layer for exposing the conductive bumps to the openings of the dielectric layer;

forming a metal layer in the openings of the dielectric layer and the resist layer for electrically connecting the conductive bumps of the chips and the conductive circuits; and

removing the resist layer, cutting along the dielectric layer between the chips and removing the carrier board for separating the chips from each other and exposing the conductive circuits from non-active surfaces of the chips.

2. The manufacturing method of claim 1, wherein the carrier board is a metal board, and the conductive circuits are formed as an Au/Ni/Au structure on the carrier board by electroplating.

3. The manufacturing method of claim 1, further comprising the steps of:

providing a wafer having the plurality of chips, wherein each chip has an active surface and a non-active surface opposing to the active surface, the solder pads are disposed on the active surface of each chip, and after a test is performed to determine each chip being a good die, conductive bumps are mounted on the solder pads of the good die;

thinning the non-active surface of the wafer for the wafer to be attached to a tape; and

singulating the wafer so as to take out the good die and mounting the good die to the carrier board, wherein an adhesive layer is interposed between the good die and the carrier board.

4. The manufacturing method of claim 1, wherein the dielectric layer is made of one of an epoxy resin and polyimide, and the resist layer is a dry film.

5. The manufacturing method of claim 1, wherein the openings in the dielectric layer at periphery of the chips are formed by one of laser and etching for exposing the part of the conductive circuits, and the openings of the dielectric layer are spaced away from sides of the chips such that the sides of the chips are covered by the dielectric layer.

6. The manufacturing method of claim 1, wherein the metal layer comprises a copper layer, a nickel layer and a solder layer, and is formed by depositing the copper layer in the openings of the dielectric layer via electroplating to cover regions from periphery of active surfaces of the chips to the conductive bumps and depositing the nickel layer and the solder layer on the copper layer.

7. The manufacturing method of claim 1, wherein a thermal compression is performed such that the metal layer on the active surface of the chip of one semiconductor device is electrically connected to the conductive circuits on the non-active surface of the chip of another semiconductor device, thereby forming a multi-chip stack structure.

8. The manufacturing method of claim 7, wherein an underfill material is filled in the spacing between the semiconductor devices of the stack structure.

9. The manufacturing method of claim 1, further comprising the steps of:

forming an insulation layer on the active surfaces of the chips and the metal layer after the metal layer is formed and the resist layer is removed; and

removing the carrier board and cutting along the dielectric layer between the chips so as to separate the chips from each other.

10. The manufacturing method of claim 9, wherein conductive components are mounted on outer surface of the conductive circuits on the non-active surface of the chips.

11. The manufacturing method of claim 10, wherein the insulation layer has openings formed to expose the metal layer, and the conductive components mounted on the conductive circuits of another semiconductor device are electrically connected to the metal layer exposed from the insulation layer.

12. A semiconductor device, comprising:

a chip having an active surface and a non-active surface opposing to the active surface, a plurality of solder pads disposed on the active surface, and conductive bumps disposed on the solder pads;

conductive circuits formed on the non-active surface of the chip;

a dielectric layer formed at sides of the chip, and having openings for exposing a part of the conductive circuits; and

a metal layer formed in the openings of the dielectric layer and at periphery of the active surface of the chip for electrically connecting the conductive bumps of the chip and the conductive circuits.

13. The semiconductor device of claim 12, wherein an adhesive layer is formed between the non-active surface of the chip and the conductive circuits, and the conductive circuits are relatively disposed at periphery of the adhesive layer.

14. The semiconductor device of claim 12, wherein the conductive circuits are formed as an Au/Ni/Au structure, the dielectric layer is made of one of an epoxy resin and polyimide, and the metal layer comprises a copper layer, a nickel layer and a solder layer.

15. The semiconductor device of claim 12, wherein the openings of the dielectric layer are spaced away from sides of the chip such that the sides of the chip are covered by the dielectric layer.

16. The semiconductor device of claim 12, wherein the metal layer on the active surface of the chip of the semiconductor device is electrically connected to the conductive circuits on the non-active surface of the chip of another semiconductor device by a thermal compression to form a multi-chip stack structure.

17. The semiconductor device of claim 16, wherein an underfill material is filled in spacing between the semiconductor devices of the stack structure.

18. The semiconductor device of claim 12, further comprising an insulation layer formed on the active surface of the chip and the metal layer.

19. The semiconductor device of claim 18, further comprising conductive components mounted on outer surface of the conductive circuits of the non-active surface of the chip.

20. The semiconductor device of claim 19, wherein the insulation layer has openings for exposing the metal layer such that conductive components mounted on the conductive circuits of another semiconductor device are electrically connected to the metal layer exposed from the openings of the insulation layer.