Level shifter using coupling phenomenon

• US 20090261884A1
• Filed: 11/07/2008
• Published: 10/22/2009
• Est. Priority Date: 04/22/2008
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Kim, Saeng Hwan
• Granted Patent: US 7,750,718 B2
• Time in Patent Office: Days
• US Class Current: 327/333
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

A level shifter removes delay, which is generated at the time of transition of an input signal level, by adjusting a size of NMOS transistors to perform pull-down and pull-up operations. The level shifter includes a coupling unit for setting up a voltage level of a first node according to a voltage level of an input signal, a first buffer for transferring an output signal by buffering a signal from the first node, and a driving unit configured to receive the input signal and the output signal and drive the first node.

Claims

1. A level shifter comprising:

a coupling unit for setting up a voltage level of a first node according to a voltage level of an input signal;

a first buffer for transferring an output signal by buffering a signal from the first node; and

a driving unit for receiving the input signal and the output signal and drive the first node.

2. The level shifter of claim 1, wherein the coupling unit includes:

a second buffer driven by a first voltage level and a ground voltage level and configured to buffer the input signal and transfer the buffered input signal to a second node; and

a coupling element connected between the first node and the second node and configured to maintain a constant voltage difference between the first node and the second node.

3. The level shifter of claim 2, wherein the coupling element is a capacitor.

4. The level shifter of claim 2, wherein the first buffer is driven by the ground voltage level and a second voltage level which is higher than the first voltage level.

5. The level shifter of claim 4, wherein the driving unit includes:

a pull-down element connected between the first node and the ground voltage level and configured to pull-down drive the first node in response to the input signal; and

a pull-up element connected between the second voltage level and the first node and configured to pull-up drive the first node in response to the output signal.

6. The level shifter of claim 5, wherein the pull-down element and the pull-up element are pull-down and pull-up MOS transistors, respectively, and wherein a size of the pull-down MOS transistor is larger than that of the pull-up MOS transistor.

7. The level shifter of claim 2, wherein the first buffer is driven by the second voltage level which is lower than the first voltage level and the ground voltage level.

8. The level shifter of claim 7, wherein the driving unit includes:

a pull-up element connected between the first voltage level and the first node and configured to pull-down drive the first node in response to the input signal; and

a pull-down element connected between the first node and the second voltage level and configured to pull-down drive the first node in response to the output signal.

9. The level shifter of claim 8, wherein the pull-down element and the pull-up element are pull-down and pull-up MOS transistors, respectively, and wherein a size of the pull-up MOS transistor is larger than that of the pull-down MOS transistor.

10. A level shifter comprising:

a first buffer for buffering an input signal and transferring the buffered input signal to a first node;

a coupling element connected between the first node and a second node and configured to maintain a constant voltage difference between the first node and the second node;

a pull-down element for pull-down driving the second node in response to the input signal;

a second buffer for outputting an output signal by buffering a signal from the second node; and

a pull-up element for pull-up driving the second node in response to the output signal.

11. The level shifter of claim 10, wherein the first buffer is driven by a first voltage level and a ground voltage level.

12. The level shifter of claim 11, wherein the second buffer is driven by the ground voltage level and a second voltage level which is higher than the first voltage level.

13. The level shifter of claim 10, wherein the coupling element is a capacitor.

14. The level shifter of claim 10, wherein the pull-down element and the pull-up element are pull-down and pull-up MOS transistors, respectively, and wherein a size of the pull-down MOS transistor is larger than that of the pull-up MOS transistor.

15. A level shifter comprising:

a first buffer for buffering an input signal and transferring the buffered input signal to a first node;

a coupling element connected between the first node and a second node and configured to maintain a constant voltage difference between the first node and the second node;

a pull-up element for pull-up driving the second node in response to the input signal;

a second buffer for outputting an output signal by buffering a signal from the second node; and

a pull-down element for pull-up driving the second node in response to the output signal.

16. The level shifter of claim 15, wherein the first buffer is driven by a first voltage level and a ground voltage level.

17. The level shifter of claim 16, wherein the second buffer is driven by the first voltage level and a second voltage level which is lower than the ground voltage level.

18. The level shifter of claim 15, wherein the coupling element is a capacitor.

19. The level shifter of claim 15, wherein the pull-down element and pull-up element are pull down and pull up MOS transistors, respectively, and wherein a size of the pull-down MOS transistor is larger than that of the pull-up MOS transistor.

20. A level shifter comprising:

a set-up unit for setting up a voltage level of a first node according to an input signal;

a first buffer for transferring an output signal by buffering a signal from the first node; and

a pull-up element for pull-up driving the first node in response to the output signal.

21. The level shifter of claim 20, wherein the set-up unit includes:

a second buffer driven by a first voltage level and a ground voltage level and configured to buffer the input signal and transfer the buffered input signal to a second node;

a coupling element connected between the first node and the second node and configured to maintain a constant voltage difference between the first node and the second node; and

a pull-down element for pull-down driving the first node in response to the input signal.

22. The level shifter of claim 21, wherein the coupling element is a capacitor.

23. The level shifter of claim 21, wherein the first buffer is driven by the ground voltage level and a second voltage level which is higher than the first voltage level.

24. The level shifter of claim 21, wherein the pull-down element and pull-up element are pull-down and pull-up MOS transistors, respectively, and wherein a size of the pull-down MOS transistor is larger than that of the pull-up MOS transistor.