INTEGRATED INDUCTOR

• US 20090261937A1
• Filed: 06/29/2009
• Published: 10/22/2009
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Lee, Tung-Hsing, Yang, Ming-Tzong, Cheng, Tao, Ko, Ching-Chung, Chan, Kuei-Ti
• Granted Patent: US 8,860,544 B2
• Time in Patent Office: Days
• US Class Current: 336/200
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated inductor includes a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers. The passivation layer has a thickness not less than about 0.8 micrometers. By eliminating copper from the integrated inductor and increasing the thickness of the passivation layer, the distance between the bottom surface of the inductor structure and the main surface of the semiconductor substrate is increased, thus the parasitic substrate coupling may be reduced and the Q-factor may be improved. Besides, the increased thickness of the aluminum layer may help improve the Q-factor as well.

Claims

1. An integrated inductor comprising a winding consisting of an aluminum layer atop a passivation layer, wherein the aluminum layer does not extend into the passivation layer and has a thickness that is not less than about 2.0 micrometers.

2. The integrated inductor according to claim 1, wherein the passivation layer has a thickness not less than about 0.8 micrometers.

3. The integrated inductor according to claim 1, wherein the integrated inductor is fabricated in an inductor region and no copper interconnection is formed within the inductor region.

4. The integrated inductor according to claim 1, wherein the aluminum layer is a redistribution layer.

5. The integrated inductor according to claim 1, wherein the winding consists of the aluminum layer only.

6. The integrated inductor according to claim 1, wherein the integrated inductor is formed in an integrated circuit device having a substrate and a plurality of metal layers, at least one of the metal layers consists of copper.

7. The integrated inductor according to claim 6, wherein none of the metal layers is formed between the integrated inductor and the substrate.

8. The integrated inductor according to claim 6, wherein a distance between a bottom surface of the integrated inductor and a main surface of the substrate is not less than a distance between a bottom surface of a topmost one of the metal layers and the main surface of the substrate.

9. The integrated inductor according to claim 6, wherein a distance between a bottom surface of the integrated inductor and a main surface of the substrate is not less than about 3.0 micrometers.

10. The integrated inductor according to claim 6, wherein at least one of top two of the metal layers consists of copper.