APPARATUS AND METHOD FOR SIGMA-DELTA ANALOG TO DIGITAL CONVERSION

• US 20090261998A1
• Filed: 04/21/2009
• Published: 10/22/2009
• Est. Priority Date: 04/21/2008
• Status: Active Grant

• Current Assignee: Industry Academic Cooperation Foundation, Samsung Electronics Co. Ltd.
• Original Assignee: Industry Academic Cooperation Foundation, Samsung Electronics Co. Ltd.
• Inventors: Han, Gunhee, Ham, Seog Heon, Chae, Youngcheol, Lee, In Hee, Cheon, Jimin
• Granted Patent: US 7,916,061 B2
• Time in Patent Office: Days
• US Class Current: 341/118
• CPC Class Codes: H03M 1/56 Input signal compared with linear ramp
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path
• CPC Class Codes: H03M 3/46 using a combination of at least one delta-sigma modulator in series with at least one analogue/digital converter of a different type

Abstract

A method and apparatus are provided for sigma-delta (ΣΔ) analog to digital conversion, the method including receiving an analog signal, sampling the received signal, comparing the sampled signal with a constant reference voltage, providing at least one high-order bit responsive to the constant reference comparison, comparing the sampled signal with a variable reference voltage, providing at least one low-order bit responsive to the variable reference comparison, and combining the at least one high-order bit with the at least one low-order bit; and the apparatus including a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least One low-order bit.

Claims

1. An analog-to-digital converter (ADC) comprising;

a first ADC unit having a comparator with a constant reference voltage for providing at least one high-order bit; and

a second ADC unit connected to the first ADC unit, the second ADC unit having a comparator with a variable reference voltage for providing at least one low-order bit.

2. An ADC as defined in claim 1, further comprising an adder in signal communication with the first and second ADC units for adding the at least one high-order bit and the at least one low-order bit.

3. An ADC as defined in claim 1 wherein the variable reference voltage has a single slope.

4. An ADC as defined in claim 3 wherein the slope of the variable reference voltage is controllable.

5. An analog-to-digital converter (ADC) comprising:

a comparator;

a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit; and

a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.

6. An ADC as defined in claim 5, further comprising an adder in signal communication with the first and second ADC portions for adding the at least one high-order bit and the at least one low-order bit.

7. An ADC as defined in claim 5 wherein the variable reference voltage has a single slope.

8. An ADC as defined in claim 7 wherein the slope of the variable reference voltage is controllable.

9. A CMOS image sensor comprising:

a pixel driver; and

an analog-to-digital converter (ADC) connected to the driver, the ADC having a comparator, a first ADC portion supplying the comparator with a constant reference voltage for providing at least one high-order bit, and a second ADC portion supplying the comparator with a variable reference voltage for providing at least one low-order bit.

10. An image sensor as defined in claim 9, further comprising an adder in signal communication with the first and second ADC portions for adding the at least one high-order bit and the at least one low-order bit.

11. An image sensor as defined in claim 9 wherein the variable reference voltage has a single slope.

12. An image sensor as defined in claim 11 wherein the slope of the variable reference voltage is controllable.

13. An analog-to-digital converting method comprising:

receiving an analog signal;

sampling the received signal;

comparing the sampled signal with a constant reference voltage;

providing at least one high-order bit responsive to the constant reference comparison;

comparing the sampled signal with a variable reference voltage;

providing at least one low-order bit responsive to the variable reference comparison; and

combining the at least one high-order bit with the at least one low-order bit.

14. A method as defined in claim 13 wherein the sampling includes over-sampling.

15. A method as defined in claim 13, further comprising:

providing at least one remainder or error signal responsive to the sampled received signal; and

re-sampling the remainder or error signal prior to comparing with the variable reference voltage.

16. A method as defined in claim 13 wherein the variable reference voltage has a single slope.

17. A method as defined in claim 16, further comprising changing the resolution by controlling the slope of the variable reference voltage.

18. An image sensing method comprising:

sensing an analog voltage signal of a sensor pixel;

sampling the sensed signal;

comparing the sampled signal with a constant reference voltage;

providing at least one high-order bit responsive to the constant reference comparison;

comparing the sampled signal with a variable reference voltage;

providing at least one low-order bit responsive to the variable reference comparison; and

combining the at least one high-order bit with the at least one low-order bit.

19. A method as defined in claim 18 wherein the sampling includes over-sampling.

20. A method as defined in claim 18, further comprising:

providing at least one remainder or error signal responsive to the sampled received signal; and

re-sampling the remainder or error signal prior to comparing with the variable reference voltage.

21. A method as defined in claim 18 wherein the variable reference voltage has a single slope.

22. A method as defined in claim 21, further comprising changing the resolution by controlling the slope of the variable reference voltage.

23. An analog-to-digital converter (ADC) device comprising:

a sigma-delta ADC for sampling an analog input signal at a first sampling rate and providing at least one upper bit of a digital output signal and an error signal; and

a single-slope ADC connected to the sigma-delta ADC for receiving the error signal and providing at least one lower bit of the digital output signal.

24. A device as defined in claim 23, the sigma-delta ADC comprising:

a sampler for receiving the analog input signal and providing an over-sampled signal at the first sampling rate;

a sigma-delta modulator connected to the sampler for receiving the over-sampled signal and providing a bit-stream signal and an error signal; and

a decimation filter connected to the sigma-delta modulator for receiving the bit-stream signal and providing at least one upper bit of the digital output signal.

25. A device as defined in claim 24, the sigma-delta modulator comprising a comparator connected to the input of the decimation filter, the comparator having an inverting input and a non-inverting input, the non-inverting input disposed for receiving a voltage reference signal.

26. A device as defined in claim 25, the sigma-delta modulator further comprising at least one integrator connected to the inverting input of the comparator.

27. A device as defined in claim 25, the sigma-delta modulator further comprising at least one digital-to-analog converter (DAC) connected to the output of the comparator.

28. A device as defined in claim 23, the single-slope ADC comprising a counter.

29. A device as defined in claim 28, the single-slope ADC further comprising a comparator connected to the input of the counter, the comparator having an inverting input and a non-inverting input, the non-inverting input disposed for receiving a voltage ramp or staircase-shaped signal.

30. A device as defined in claim 29, the single-slope ADC further comprising a sampler connected between the sigma-delta ADC and the inverting input of the comparator, the sampler disposed for receiving the error signal and providing a sampled error signal at a second sampling rate.

31. A device as defined in claim 23 wherein the sigma-delta ADC and the single-slope ADC switchably share a comparator.

32. A device as defined in claim 23 wherein the sigma-delta ADC and the single-slope ADC share a sampler.

33. An analog-to-digital converting method comprising:

sampling an analog input signal at a first sampling rate and providing at least one upper bit of a digital output signal and an error signal; and

providing at least one lower bit of the digital output signal responsive to the error signal.

34. A method as defined in claim 33, further comprising:

receiving the analog input signal and providing an over-sampled signal at the first sampling rate;

providing a bit-stream signal and an error signal responsive to the over-sampled signal; and

providing the at least one upper bit of the digital output signal responsive to the bit-stream signal.

35. A method as defined in claim 34, further comprising decimating the bit-stream signal to provide the at least one upper bit of the digital output signal.

36. A method as defined in claim 34, further comprising:

integrating the over-sampled signal;

receiving a voltage reference signal; and

comparing the voltage reference signal with the integrated signal to provide the bit-stream signal.

37. A method as defined in claim 36, further comprising:

converting the bit-stream signal into an analog signal; and

subtracting the converted signal from the over-sampled signal prior to integration.

38. A method as defined in claim 33, further comprising counting a signal responsive to the error signal to provide the at least one lower bit of the digital output signal.

39. A method as defined in claim 38, further comprising:

receiving a voltage ramp or staircase-shaped signal; and

comparing the error signal with the voltage ramp or staircase-shaped signal to provide the signal responsive to the error signal for counting.

40. A method as defined in claim 39, further comprising sampling the error signal and providing a sampled error signal at a second sampling rate before comparing.

41. A method as defined in claim 33, further comprising switching between providing the at least one upper bit of the digital output signal and providing the at least one lower bit of the digital output signal by switching the inputs and output of a single comparator.

42. A method as defined in claim 41, further comprising:

switching the inverting input of the single comparator between an integrated over-sampled signal and an error signal, respectively;

switching the non-inverting input of the single comparator between a voltage reference signal and a voltage staircase signal, respectively; and

switching the output of the single comparator between a bit-stream signal and a compared signal, respectively.

43. A method as defined in claim 42, further comprising:

decimating the switched bit-stream signal to provide the at least one upper bit of the digital output signal; and

counting the compared signal to provide the at least one lower bit of the digital output signal.

44. A multi-media system comprising:

at least one input/output device; and

a multi-media processor connected to the at least one input/output device, the multi-media processor having a sigma-delta analog-to-digital converter (ADC) for sampling an analog input signal at a first sampling rate and providing at least one upper bit of a digital output signal and an error signal, and a single-slope ADC connected to the sigma-delta ADC for receiving the error signal and providing at least one lower bit of the digital output signal.

45. A system as defined in claim 44 wherein the sigma-delta ADC and the single-slope ADC switchably share a comparator

46. A CMOS image sensor comprising:

a pixel array;

a driver connected to the pixel array; and

an analog-to-digital converter (ADC) unit connected to the driver, the ADC unit having a sigma-delta ADC for sampling an analog input signal at a first sampling rate and providing at least one upper bit of a digital output signal and an error signal, and a single-slope ADC connected to the sigma-delta ADC for receiving the error signal and providing at least one lower bit of the digital output signal.

47. A CMOS image sensor as defined in claim 46 wherein the sigma-delta ADC and the single-slope ADC switchably share a comparator.