×

FLOATING GATE MEMORY DEVICE WITH INTERPOLY CHARGE TRAPPING STRUCTURE

  • US 20090262583A1
  • Filed: 03/24/2009
  • Published: 10/22/2009
  • Est. Priority Date: 04/18/2008
  • Status: Active Grant
First Claim
Patent Images

1. A memory cell comprising:

  • a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region;

    a multilayer stack over the channel including a first tunneling barrier structure disposed on the surface of the substrate above the channel region, a floating gate disposed above the first tunneling barrier structure and above the channel region, a second tunneling barrier structure above the floating gate, a charge trapping dielectric layer above the second tunneling barrier structure and above the channel region, and a top dielectric structure disposed above the charge trapping dielectric layer; and

    a top conductive layer disposed above the top dielectric structure and above the channel region;

    wherein the second tunneling barrier structure has a different electron tunneling probability function than the first tunneling barrier structure for electron tunneling than the first tunneling barrier structure under bias conditions applied to program the memory cell.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×