FLOATING GATE MEMORY DEVICE WITH INTERPOLY CHARGE TRAPPING STRUCTURE

• US 20090262583A1
• Filed: 03/24/2009
• Published: 10/22/2009
• Est. Priority Date: 04/18/2008
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting
• Granted Patent: US 8,068,370 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/4234 Gate electrodes for transistors with charge trapping gate insulator
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A charge trapping floating gate is described with asymmetric tunneling barriers. The memory cell includes a source region and a drain region separated by a channel region. A first tunneling barrier structure is disposed above the channel region. A floating gate is disposed above the first tunneling barrier structure covering the channel region. A second tunneling barrier is disposed above the floating gate. A dielectric charge trapping structure disposed above the second tunneling barrier and a blocking dielectric structure is disposed above the charge trapping structure. A top conductive layer disposed above the top dielectric structure acts as a gate. The second tunneling barrier is a more efficient conductor of tunneling current, under bias conditions applied for programming and erasing the memory cell, than the first tunneling barrier structure.

Claims

1. A memory cell comprising:

a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region;

a multilayer stack over the channel including a first tunneling barrier structure disposed on the surface of the substrate above the channel region, a floating gate disposed above the first tunneling barrier structure and above the channel region, a second tunneling barrier structure above the floating gate, a charge trapping dielectric layer above the second tunneling barrier structure and above the channel region, and a top dielectric structure disposed above the charge trapping dielectric layer; and

a top conductive layer disposed above the top dielectric structure and above the channel region;

wherein the second tunneling barrier structure has a different electron tunneling probability function than the first tunneling barrier structure for electron tunneling than the first tunneling barrier structure under bias conditions applied to program the memory cell.

2. The memory cell of claim 1, wherein the first tunneling barrier structure comprises a layer of silicon oxide between 7 and 4 nanometers thick.

3. The memory cell of claim 1, wherein the second tunneling barrier structure comprises a combination of materials, and is arranged to establish a relatively low valence band energy level near the channel surface, and an increase in valence band energy level at a first distance from the channel surface and a decrease in valence band energy at a second distance more than 2 nanometers from the channel surface.

4. The memory cell of claim 1, wherein the second tunneling barrier structure comprises a first silicon oxide layer adjacent the floating gate and having a thickness of 18 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a second oxide layer on the silicon nitride layer having a thickness of 35 Å

or less.

5. The memory cell of claim 1, wherein the second tunneling barrier structure comprises a barrier engineered tunneling barrier structure.

6. The memory cell of claim 1, wherein the floating gate comprises a semiconductor layer less than 10 nanometers thick.

7. The memory cell of claim 1, wherein the top dielectric structure comprises a first layer having a dielectric constant κ

₁ contacting the charge trapping dielectric layer and a second layer contacting the top conductive layer, the second layer having a dielectric constant κ

₂ higher than κ

₁ of the first layer, and the second layer having thickness less than κ

₂/κ

₁ times that of the first layer.

8. The memory cell of claim 7, wherein the first layer comprises silicon oxide or silicon oxynitride, the second layer comprises aluminum oxide, and the charge trapping dielectric layer comprises at least one of silicon nitride and silicon oxynitride.

9. The memory cell of claim 7, wherein the dielectric constant κ

₂ of the second layer is greater than 7.

10. The memory cell of claim 1, wherein the charge trapping dielectric layer comprises silicon nitride.

11. The memory cell of claim 1, including control circuitry coupled to the memory cell, the control circuitry including a program mode in which a bias condition is applied to the memory cell to induce tunneling between the channel to the floating gate, and between the floating gate and the charge trapping dielectric layer to increase negative charge trapped, and an erase mode in which a bias condition is applied to induce tunneling between the charge trapping dielectric layer and the floating gate and between the floating gate and the channel to decrease negative charge trapped.

12. A memory cell comprising:

a semiconductor body having a surface and a channel region;

a multilayer stack over the semiconductor body including a floating gate and a charge trapping dielectric layer above the floating gate, a top dielectric structure disposed above the charge trapping dielectric layer, and means for enabling electrons to move from the semiconductor body through the floating gate to the charge trapping dielectric layer under positive gate bias conditions applied for increasing a threshold voltage, while preventing electron tunneling from the charge trapping dielectric layer through the floating gate to the semiconductor body under bias conditions applied for reading; and

a top conductive layer disposed above the top dielectric structure and above the channel region.

13. The memory cell of claim 12, including control circuitry coupled to the memory cell, the control circuitry including a program mode in which a bias condition is applied to the memory cell to induce tunneling between the channel region to the floating gate, and between the floating gate and the charge trapping dielectric layer to increase negative charge trapped, and an erase mode in which a bias condition is applied to induce tunneling between the charge trapping dielectric layer and the floating gate and between the floating gate and the channel region to decrease negative charge trapped.

14. A memory cell comprising:

a semiconductor substrate having a surface with a source region and a drain region in the substrate and separated by a channel region;

a gate dielectric comprising silicon oxide between 7 and 4 nanometers thick disposed on the surface of the substrate above the channel region,

a semiconductor floating gate above the gate dielectric and above the channel region;

a tunneling barrier structure above the floating gate, the tunneling barrier structure including a first silicon oxide layer adjacent the floating gate and having a thickness of 18 Å

or less, a silicon nitride layer on the first silicon oxide layer having a thickness of 30 Å

or less, and a second oxide layer on the silicon nitride layer having a thickness of 35 Å

or less;

a charge trapping dielectric layer between 4 and 7 nanometers thick above the tunneling barrier structure;

a blocking dielectric structure disposed above the charge trapping dielectric layer; and

a top conductive layer disposed above the blocking dielectric structure.

15. The memory cell of claim 14, wherein the blocking dielectric structure comprises a first layer having a dielectric constant κ

₁ contacting the charge trapping dielectric layer and a second layer contacting the top conductive layer, the second layer having a dielectric constant κ

₂ higher than κ

₁ of the first layer, and the second layer having thickness less than κ

₂/κ

₁ times that of the first layer.

16. The memory cell of claim 14, wherein the floating gate comprises a semiconductor layer less than 10 nanometers thick.

17. A method for manufacturing an integrated circuit, comprising:

forming a gate dielectric layer on semiconductor substrate;

forming a patterned polysilicon layer over the gate dielectric layer, including a first pattern in a memory area region on the substrate and a second pattern in a peripheral region on the substrate;

forming a multilayer dielectric stack over the patterned polysilicon layer, the multilayer dielectric stack comprising a tunneling barrier structure in contact with the patterned polysilicon layer, a charge trapping dielectric layer above the tunneling barrier layer, and a top dielectric structure disposed above the charge trapping dielectric layer;

opening contact openings through the multilayer dielectric stack to expose the patterned polysilicon layer at selected locations in the peripheral region;

forming a patterned conductor over the multilayer dielectric stack, and contacting the patterned polysilicon layer through the contact openings at the selected locations; and

forming source and drain regions in the substrate adjacent the patterned conductor.

18. The method of claim 17, wherein the tunneling barrier structure has a greater tunneling efficiency for charge tunneling than the gate dielectric layer under bias conditions applied for program and erase operations.

19. The method of claim 17, wherein the gate dielectric layer comprises silicon oxide having a thickness between 4 and 7 nanometers.

20. The method of claim 17, wherein the forming a tunneling barrier structure comprises forming a bandgap engineered tunneling barrier structure including a plurality of dielectric layers.

21. The method of claim 17, wherein the patterned conductor layer comprises polysilicon.

22. The method of claim 17, including etching the patterned polysilicon layer in the memory area to provide floating gates.

23. The method of claim 17, wherein the top dielectric structure comprises silicon dioxide having a thickness in the range of 5 to 9 nanometers.

24. (canceled)