Computation spreading utilizing dithering for spur reduction in a digital phase lock loop
First Claim
1. A method of reducing the generation of frequency spurs in the performance of a processing task normally performed within a reference clock period, said method comprising the steps of:
- dividing said task into a plurality of atomic operation computations for execution in a software loop;
randomizing the execution of one or more atomic operations in each iteration of said software loop; and
wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock.
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Abstract
A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum. Further reduction in spurs is achieved by dithering the duration of the software loop of atomic operations and/or by randomly shuffling one or more non-data dependent instructions within each iteration of the software loop.
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Citations
36 Claims
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1. A method of reducing the generation of frequency spurs in the performance of a processing task normally performed within a reference clock period, said method comprising the steps of:
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dividing said task into a plurality of atomic operation computations for execution in a software loop; randomizing the execution of one or more atomic operations in each iteration of said software loop; and wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of reducing the generation of frequency spurs in a software based digital phase locked loop normally performed within a reference clock period, said method comprising the steps of:
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dividing computation of said phase locked loop operation into a plurality of atomic operation computations for execution in a software loop; dithering the duration of each iteration of said software loop; and wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A method of reducing the generation of frequency spurs in a software based digital phase locked loop normally performed within a reference clock period, said method comprising the steps of:
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dividing computation of said phase locked loop operation into a plurality of atomic operation computations for execution in a software loop; dithering the duration of each iteration of said software loop by inserting a plurality of random wait periods throughout said software loop; and wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A method of reducing the generation of frequency spurs in a software based digital phase locked loop normally performed within a reference clock period, said method comprising the steps of:
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dividing computation of said phase locked loop operation into a plurality of atomic operation computations for execution in a software loop; randomly shuffling the order of execution of one or more atomic operations in each iteration of said software loop; and wherein said atomic operations are clocked using a processor clock having a frequency significantly higher than that of said reference clock. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. A phase locked loop (PLL) having a reference clock, said PLL comprising:
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means for partitioning computation of said phase locked loop into a plurality of atomic operation computations for execution in a software loop; means for randomizing the execution of one or more atomic operations in each iteration of said software loop; a processor clock having a frequency significantly higher than that of said reference clock; an oscillator operative to generate a radio frequency (RF) signal having a frequency determined in accordance with a tuning command input thereto; and a processor operative to generate said tuning command, said processor clocked at said processor clock rate, said processor comprising a calculation unit operative to execute instructions, wherein each instruction is operative to perform one of said atomic operation computations. - View Dependent Claims (31, 32, 33, 34, 35, 36)
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Specification