METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

• US 20090263943A1
• Filed: 06/26/2009
• Published: 10/22/2009
• Est. Priority Date: 03/14/1997
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Fukada, Shinichi, Suzuki, Masayuki, Hashimoto, Naotaka, Ikeda, Shuji, Nishihara, Shinji, Momiji, Hiroshi, Abe, Hiromi
• Granted Patent: US 8,034,715 B2
• Time in Patent Office: Days
• US Class Current: 438/197
• CPC Class Codes: C23C 14/16 on metallic substrates or on substrates of boron or silicon
• CPC Class Codes: C23C 14/3414 Metallurgical or chemical aspects of target preparation, e.g. casting, powder metallurgy
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/31608 Deposition of SiO2 H01L21/31625, H01L21/31629 and H01L21/31633 take precedence
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823835 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Claims

1. A method of fabricating a semiconductor integrated circuit device, comprising:

(a) forming a gate electrode over a silicon surface of a wafer, the gate electrode having a silicon film to be a poly-silicon conductive film;

(b) forming a source region and a drain region over the silicon surface of the wafer;

(c) depositing a Co film on the source region, the drain region and the gate electrode, by sputtering, from a Co sputtering target which, apart from carbon and oxygen impurities, is at least 99.99 wt. % pure, and wherein a sum of Fe and Ni in the Co sputtering target is not greater than 50 ppm by weight;

(d) performing a first rapid thermal annealing at a first temperature to a surface covered with the Co film so as to form Co monosilicide film;

(e) removing a remaining Co film not formed into Co monosilicide in the step (d); and

(f) after step (e), performing a second rapid thermal annealing at a second temperature higher than the first temperature to a surface covered with the Co monosilicide film so as to form Co disilicide film.

2. A method of fabricating a semiconductor integrated circuit device according to claim 1, wherein the first temperature is not higher than 525°

C.

3. A method of fabricating a semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is designed under design rules not larger than 0.25 micro-meter.

4. A method of fabricating a semiconductor integrated circuit device according to claim 3, wherein the Co sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.

5. A method of fabricating a semiconductor integrated circuit device according to claim 3, wherein said Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.

6. A method of fabricating a semiconductor integrated circuit device according to claim 3, wherein said Co film is deposited with a thickness of 18-60 nm.

7. A method of fabricating a semiconductor integrated circuit device according to claim 3, wherein the second temperature is from 650°

C. to 800°

C.

8. A method of fabricating a semiconductor integrated circuit device according to claim 7, wherein the first temperature is not lower than 475°

C.

9. A method of fabricating a semiconductor integrated circuit device according to claim 8, wherein the Co sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.

10. A method of fabricating a semiconductor integrated circuit device according to claim 8, wherein said Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.

11. A method of fabricating a semiconductor integrated circuit device according to claim 7, wherein the Co sputtering target includes a sum of Fe and Ni which is not greater than 10 ppm by weight.

12. A method of fabricating a semiconductor integrated circuit device according to claim 7, wherein said Co sputtering target, apart from carbon and oxygen impurities, is 99.999 wt. % pure.

13. A method of fabricating a semiconductor integrated circuit device according to claim 3, wherein the first temperature is not lower than 475°

C.

14. A method of fabricating a semiconductor integrated circuit device according to claim 3, wherein each junction depth of the source region and the drain region is between 0.2 and 0.1 micro-meter.