Multiphase Clocking Systems with Ring Bus Architecture

• US 20090265498A1
• Filed: 04/21/2008
• Published: 10/22/2009
• Est. Priority Date: 04/21/2008
• Status: Active Grant

• Current Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Original Assignee: Toshiba America Electronic Components Incorporated (Toshiba Corporation)
• Inventors: Yamaoka, Hiroaki
• Granted Patent: US 8,122,279 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction. Controllers within the processor cores provide phase-shifted signals to the latches to clock data into them. Data transfers on the bus may be controlled by an arbiter which is coupled to the processor cores'"'"' controllers. The arbiter may schedule data transfers on the bus based on data transfer speeds associated with left-to-right and right-to-left data transfer directions. The arbiter may cause the phases of the clock signals to be selectively varied, or may cause the clock signals to be gated.

Claims

1. A system comprising:

a plurality of digital circuit components;

a ring bus which includes a plurality of latches, wherein each of the latches is coupled to a corresponding one of the digital circuit components to enable the digital circuit components to transmit and receive data on the bus; and

a timing system which is configured

to generate a plurality of clock signals, wherein each of the clock signals is phase-shifted with respect to the remainder of the clock signals, and

to provide each of the clock signals to a different one of the digital circuit components;

wherein each of the latches is clocked based on the clock signal provided to the digital circuit component associated with the latch.

2. The system of claim 1:

wherein the system comprises a multiprocessor and the digital circuit components comprise processor cores, wherein each of the processor cores includes a controller that receives the clock signal associated with the processor core, wherein the controller is coupled to the latch associated with the processor core; and

wherein the ring bus comprises a bidirectional ring bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction;

further comprising an arbiter coupled to each of the processor cores and configured to control data transfers on the ring bus, wherein the arbiter is configured to provide the clock signals to the processor cores in a manner that causes non-adjacent ones of the processor cores to be fired consecutively, and wherein the arbiter is coupled to each controller and is configured to cause each controller to selectively modify the received clock signal and to provide the modified clock signal to the associated latch.

3. The system of claim 1, wherein the ring bus comprises a bidirectional ring bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction.

4. The system of claim 1, wherein the system comprises a multiprocessor and the digital circuit components comprise processor cores.

5. The system of claim 1, further comprising an arbiter coupled to each of the digital circuit components and configured to control data transfers on the ring bus.

6. The system of claim 5, wherein the arbiter is configured to schedule data transfers on the ring bus based at least in part on data transfer speeds associated with clockwise and counterclockwise data paths of the ring bus.

7. The system of claim 5, wherein the arbiter is configured to provide the clock signals to the digital circuit components in a manner that causes non-adjacent ones of the digital circuit components to be fired consecutively.

8. The system of claim 5, wherein the arbiter is configured to cause the phase of each of the clock signals to be selectively varied.

9. The system of claim 5, wherein the arbiter is configured to cause each of the clock signals to be selectively gated.

10. The system of claim 5, wherein each of the digital circuit components includes a controller that receives the clock signal associated with the digital circuit component, wherein each controller is coupled to the latch associated with the digital circuit component, and wherein the arbiter is coupled to each controller and is configured to cause the controller to modify the clock signal received by the controller and to provide the modified clock signal to the associated latch.

11. The system of claim 1, further comprising one or more peripheral components that are coupled to the ring bus and are configured to transmit and receive data on the bus.

12. A method implemented in a system having a plurality of digital circuit components coupled to corresponding latches in a ring bus, the method comprising:

generating a plurality of clock signals, wherein each of the clock signals is phase-shifted with respect to the remainder of the clock signals;

providing each of the clock signals to a different one of the digital circuit components; and

clocking data into the latch corresponding to one of the digital circuit components based on the clock signal provided to the digital circuit component.

13. The method of claim 12, further comprising scheduling one or more data transfers on the ring bus based at least in part on data transfer speeds associated with clockwise and counterclockwise data paths of the ring bus.

14. The method of claim 12, further comprising providing the clock signals to the digital circuit components in a manner that causes non-adjacent ones of the digital circuit components to be fired consecutively.

15. The method of claim 12, further comprising selectively varying the phase of each of the clock signals.

16. The method of claim 12, further comprising selectively gating each of the clock signals and providing the selectively gated clock signals to the latches.

17. The method of claim 16, further comprising performing the selective gating of the clock signals in a plurality of controllers, wherein each controller is associated with a corresponding one of the digital circuit components.

18. A multiprocessor comprising:

a plurality of processor cores;

a timing system which is configured

to generate a plurality of clock signals at a single clock frequency, wherein each of the clock signals is phase-shifted with respect to the remainder of the clock signals, and

to provide each of the clock signals to a different one of the processor cores; and

a bidirectional ring bus which includes a plurality of latches, wherein each of the latches is coupled to a corresponding one of the processor cores to enable the processor cores to transmit and receive data on the bus, wherein each of the latches is clocked by the clock signal provided to the processor core associated with the latch, and wherein data is transferred between consecutive ones of the latches in an amount of time that is less than a clock period of the clock signals.

19. The multiprocessor of claim 18, wherein the timing system is configured to vary the phase shift of each of the clock signals.

20. The multiprocessor of claim 18, further comprising:

a plurality of controllers, wherein each of the controllers is associated with one of the processor cores and is coupled to the latch associated with the processor core; and

an arbiter coupled to the controllers, wherein data transfers on the ring bus are controlled by the arbiter.