Information Processing Apparatus, Information Processing Method, and Computer Program

• US 20090265500A1
• Filed: 03/11/2009
• Published: 10/22/2009
• Est. Priority Date: 04/21/2008
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kyusojin, Hiroshi
• Granted Patent: US 8,166,339 B2
• Time in Patent Office: Days
• US Class Current: 710/308
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.

Claims

1. An information processing apparatus comprising:

a plurality of nodes, each node connecting at least a memory and a processor to a system bus;

an interconnection bus that interconnects the nodes;

a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and

a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.

2. The information processing apparatus according to claim 1, wherein the memory selecting unit selects, if reservation of the memory connected to the system bus to which the device is connected has failed, a memory other than the memory connected to the system bus to which the device is connected as the memory to be accessed by the device.

3. The information processing apparatus according to claim 1, wherein the memory selecting unit terminates, if reservation of the memory connected to the system bus to which the device is connected has failed, processing performed by the device.

4. The information processing apparatus according to claim 1, wherein the memory selecting unit repeats, if reservation of the memory connected to the system bus to which the device is connected has failed, reservation of the memory connected to the system bus to which the device is connected.

5. The information processing apparatus according to claim 1, further comprising a processor selecting unit that selects a processor connected to the system bus to which the device is connected as a processor on which a device driver corresponding to the device is set.

6. The information processing apparatus according to claim 5, wherein the device selecting unit determines the system bus to which the device is connected and selects the processor connected to the system bus as a processor on which an application using the device is activated.

7. The information processing apparatus according to claim 1, wherein the device driver is split into a main processing performing portion that performs main data processing and an interrupt processing performing portion that performs interrupt processing, and

wherein a first processor that is one of a plurality of processors set to the plurality of nodes is the main processing performing processor, and a second processor that is different from the first processor is the interrupt processing performing processor.

8. The information processing apparatus according to claim 7, wherein the interrupt processing performing processor selects a processor using any one of the following selecting schemes including:

selecting a processor connected to the system bus to which the device is connected;

selecting a processor with the lowest load at a point of time at which the processor is to be selected; and

selecting a processor using the round-robin scheme.

9. The information processing apparatus according to claim 7, wherein the device is a device that performs communication processing, and

wherein the main processing unit is a processing unit that performs data sending completion processing, data reception completion processing, and error processing.

10. An information processing method performed by an information processing apparatus, the information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus, an interconnection bus that interconnects the nodes, and a device that is connected to a system bus on any of the plurality of nodes and performs data processing, the method comprising the step of:

selecting, with a memory selecting unit, a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.

11. A computer program for causing an information processing apparatus to perform information processing, the information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus, an interconnection bus that interconnects the nodes, and a device that is connected to a system bus on any of the plurality of nodes and performs data processing, the computer program comprising the step of:

causing a memory selecting unit to select a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.