SOLID STATE DISK CONTROLLER APPARATUS

• US 20090265513A1
• Filed: 06/25/2009
• Published: 10/22/2009
• Est. Priority Date: 01/11/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: RYU, Dong-Ryul
• Granted Patent: US 8,159,889 B2
• Time in Patent Office: Days
• US Class Current: 711/149
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.

Claims

1. A solid state drive controller comprising:

a first data transfer block connected to a first port;

a second data transfer block connected to a second port; and

a central processing unit connected to the first and second data transfer blocks through a CPU bus,

wherein data is transferred between the first port and the second port through the first and second data transfer blocks bypassing the CPU bus based on a control of the central processing unit.

2. The solid state drive controller of claim 1, wherein the first data transfer block is configured to receive a command from the first port and communicate the received command to the central processing unit through the CPU bus bypassing a data transfer path provided between the first and second data transfer blocks.

3. The solid state drive controller of claim 2, wherein the first data transfer block comprises a first register,

wherein the first data transfer block is configured to store the received command into a register, and

wherein the central processing unit is configured to read the command stored in the register through the CPU bus.

4. The solid state drive controller of claim 3, wherein the central processing unit is configured to communicate the read command to the second data transfer block bypassing the data path provided by the first and second data transfer blocks.

5. The solid state drive controller of claim 4, wherein the second data transfer block comprises a second register, and wherein the central processing unit is configured to write the read command into the second register.

6. The solid state drive controller of claim 1, further comprising a buffer memory electrically connected between the first and second data transfer blocks, and configured to store the data transferred between the first and second ports.

7. The solid state drive controller of claim 6, wherein the data transferred from the first or second data transfer block is stored into the buffer memory, and the data read from the buffer memory is transferred to the first or second data transfer block.

8. The solid state drive controller of claim 7, further comprising a buffer controller/arbiter block configured to transfer the data between the first and second data transfer blocks bypassing the CPU bus, and further configured to control read and write operations of the buffer memory.

9. The solid state drive controller of claim 8, wherein the buffer controller/arbiter block is configured to control the read and write operations of the buffer memory based on a control of the central processing unit through the CPU bus.

10. The solid state drive controller of claim 1, wherein the first port is configured to be electrically coupled to an external host.

11. The solid state drive controller of claim 10, wherein the first data transfer block comprises:

a host interface control block configured to communicate data and commands with the external host through the first port; and

a FIFO configured to provide a data transfer path between the host interface control block and the buffer controller/arbiter block bypassing the CPU bus.

12. The solid state drive controller of claim 1, wherein the second port is configured to be electrically coupled to a plurality of semiconductor memories through a plurality of channels.

13. The solid state drive controller of claim 12, wherein the second data transfer block is configured to detect types of the semiconductor memories.

14. The solid state drive controller of claim 12, wherein the second data transfer block is configured to control read and write operations of the plurality of semiconductor memories based on either one of a hardware and software interleave protocol when read and write operations are requested to the plurality of channels.

15. The solid state drive controller of claim 12, wherein the second data transfer block comprises:

a memory interface control block configured to communicate data with the plurality of semiconductor memories; and

a plurality of FIFOs corresponding to the plurality pf channels respectively, and configured to provide a plurality of data transfer paths between the memory interface control block and the buffer controller/arbiter block bypassing the CPU bus.

16. The solid drive controller of claim 15, wherein the memory interface control block comprises:

a control logic configured to generate a first clock signal to be transferred to a selected semiconductor memory of the plurality of semiconductor memories through the second port, the selected semiconductor memory outputting data in synchronization with the first clock signal;

a delay circuit configured to delay the first clock signal and generate a second clock signal; and

a data fetch register configured to fetch the data from the semiconductor memory in synchronization with the second clock signal.

17. The solid state drive controller of claim 12, further comprising a plurality of ECC blocks corresponding to the plurality of channels respectively, the plurality of ECC blocks configured to detect errors of data transferred through the plurality of channels bypassing the CPU bus, and to generate error correction codes of data transferred to the plurality of semiconductor memories bypassing the CPU bus.

18. The solid state drive controller of claim 1, wherein the first data transfer block includes a serial ATA protocol.

19. A method of operating a solid state drive controller, comprising:

receiving a command from a first port;

communicating the received command to a central processing unit through a CPU bus;

transferring data between the first and a second ports bypassing the CPU bus in response to the received command.

20. The method of claim 19, wherein the transferring the data comprises:

storing the data transferred from the first port or second port into a buffer memory; and

transferring the data read from the buffer memory to the first port or the second port.