SYSTEM AND METHOD OF PREDICTING PROBLEMATIC AREAS FOR LITHOGRAPHY IN A CIRCUIT DESIGN

• US 20090265679A1
• Filed: 04/17/2008
• Published: 10/22/2009
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: International Business Machines Corporation
• Inventors: Brunner, Timothy A., Greco, Stephen E., Liegl, Bernhard R., Xiang, Hua
• Granted Patent: US 8,001,495 B2
• Time in Patent Office: Days
• US Class Current: 716/56
• CPC Class Codes: G03F 1/36 Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A system and method is provided which predicts problematic areas for lithography in a circuit design, and more specifically, which uses modeling data from a modeling tool to accurately predict problematic lithographic areas. The method includes identifying surface heights of plurality of tiles of a modeled wafer, and mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

Claims

1. A method of predicting problematic areas for lithography comprising:

identifying surface heights of a plurality tiles of a modeled wafer; and

mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the plurality of tiles.

2. The method of claim 1, wherein the average distance of the surface heights of the plurality of fields of exposure for each tile is a three dimensional representation of the surface texture at a location on the modeled wafer.

3. The method of claim 1, wherein the identifying surface heights determines a three dimensional texture of the modeled wafer.

4. The method of claim 1, wherein the identifying is performed by a modeling tool prior to reticle and wafer fabrication.

5. The method of claim 1, further comprising predicting an average distance of the surface heights of a plurality of fields of exposure for each of the plurality of tiles comprises calculating a predetermined number of focal planes for each tile in a reticle field.

6. The method of claim 5, wherein each of the predetermined number of focal planes contributes to an equal percentage of exposure dose for an entire tile.

7. The method of claim 5, wherein the predetermined number of focal planes are used to measure surface irregularity in three dimensions.

8. The method of claim 5, wherein the predetermined number of focal planes are different planes of exposure.

9. The method of claim 5, wherein each of the plurality of fields of exposure is calculated to find an average focus offset by calculating an average distance along an axis of illumination from a best average focal plane.

10. The method of claim 1, further comprising identifying tiles with an average focus offset with a value above a certain specification distance related to a depth of focus for a lithography process.

11. The method of claim 10, further comprising providing the calculated average offset data to a mask tool.

17. The method of claim 16, further comprising repeating the steps of claim 1.

12. A method, comprising:

calculating a plane which best fits modeled surface height data for a predetermined number of values within a slit;

calculating a distance along the axis of illumination distances of each tile within the slit from the calculated plane; and

identifying tiles which are above a certain specification related to a depth of focus for a lithography process based on the calculated distance along the axis of illumination.

13. The method of claim 12, wherein the identified tiles are identified as design areas which will be prone to lithography problems at subsequent lithography levels.

14. The method of claim 12, further comprising calculating an average focus offset by calculating an average distance along the axis of illumination from many planes which contribute to its exposure, and identifying the tiles with an average focus offset with a value above a certain specification distance which is related to a depth of focus for the lithography process.

15. The method of claim 12, wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities.

16. The method of claim 12, wherein the identified tiles are fixed by changing a chip design by adjusting at least one of metal patterns and densities in other tiles at a level at which a prediction is performed or at one or more underlying metal levels.

18. The method of claim 12, wherein critical images are removed in the identified tiles at a higher level.

19. The method of claim 12, wherein the identifying is performed by finding the plane which minimizes a sum of the orthogonal distances or a sum of the squares of the orthogonal distances from the plane.

20. The method of claim 12, wherein the calculating orthogonal distances is performed at a center of each tile, or to a furthest edge or corner of each tile.

21. A computer program product comprising a computer usable medium having readable program code embodied in the medium, the computer program product includes at least one component to:

identify surface heights of one or more tiles of a modeled wafer; and

mathematically mimicking a lithographic tool to determine best planes of focus for exposure for the one or more tiles.

22. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

calculating a plane which best fits modeled surface height data for a predetermined number of values within a slit;

calculating a distance along the axis of illumination distances of each tile within the slit from the calculated plane; and

identifying tiles which are above a certain specification related to a depth of focus for a lithography process based on the calculated distance along the axis of illumination.

23. The design structure of claim 22, wherein the design structure comprises a netlist.

24. The design structure of claim 22, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

25. The design structure of claim 22, wherein the design structure resides in a programmable gate array.