THIN FILM TRANSISTOR

• US 20090267067A1
• Filed: 04/21/2009
• Published: 10/29/2009
• Est. Priority Date: 04/25/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: JINBO, Yasuhiro, YOKOI, Tomokazu
• Granted Patent: US 8,049,215 B2
• Time in Patent Office: Days
• US Class Current: 257/57
• CPC Class Codes: H01J 37/32018 Glow discharge
• CPC Class Codes: H01J 37/32091 the radio frequency energy being capacitively coupled to the plasma
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor has a gate electrode; a gate insulating layer provided so as to cover the gate electrode layer; a pair of impurity semiconductor layers forming source and drain regions which is provided so that at least part of each of them overlaps the gate electrode layer and which are provided with a space therebetween; a microcrystalline semiconductor layer provided over the gate insulating layer in part of a channel length; a semiconductor layer provided over the gate insulating layer so as to cover at least the microcrystalline semiconductor layer; and an amorphous semiconductor layer provided between the semiconductor layer and the pair of impurity semiconductor layers. An impurity element which reduces the coordination number of silicon and generates dangling bonds is made to exist in the semiconductor layer.

Claims

1. A semiconductor device comprising:

a gate insulating layer over a gate electrode layer;

a microcrystalline semiconductor layer which is on and in direct contact with the gate insulating layer and overlaps the gate electrode layer;

a semiconductor layer over and in direct contact with the gate insulating layer so as to cover the microcrystalline semiconductor layer;

an amorphous semiconductor layer on and in direct contact with the semiconductor layer; and

a pair of impurity semiconductor layers forming a source region and a drain region, on and in direct contact with the amorphous semiconductor layer,

wherein at least part of each of the pair of impurity semiconductor layers overlaps the gate electrode layer,

wherein at least part of the microcrystalline semiconductor layer is provided in part of a channel, and wherein the semiconductor layer includes a plurality of crystalline regions existing in a dispersed manner in an amorphous structure.

2. The semiconductor device according to claim 1, wherein the microcrystalline semiconductor layer contains phosphorus.

3. The semiconductor device according to claim 1, wherein at least one of the plurality of crystalline regions has a grain with an inverted-conical or inverted-pyramidal structure, growing substantially radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer, in a region not reaching the pair of impurity semiconductor layers.

4. The semiconductor device according to claim 1,

wherein the semiconductor layer contains, in the vicinity of an interface with the gate insulating layer, a first impurity element reducing a coordination number of a semiconductor and generating dangling bonds and a second impurity element generating dangling bonds less easily than the first impurity element, and

wherein a concentration of the first impurity element is smaller than that of the second impurity element by one digit.

5. The semiconductor device according to claim 4, wherein the first impurity element is oxygen and the second impurity element is nitrogen.

6. The semiconductor device according to claim 5, wherein the concentration of nitrogen in the semiconductor layer decreases monotonously from a first side in direct contact with the gate insulating layer to a second side in direct contact with the amorphous semiconductor layer.

7. The semiconductor device according to claim 1, wherein the amorphous semiconductor layer is an amorphous silicon layer.

8. A semiconductor device comprising:

a gate insulating layer over a gate electrode layer;

a microcrystalline semiconductor layer which is on and in direct contact with the gate insulating layer and overlaps the gate electrode layer;

a semiconductor layer over and in direct contact with the gate insulating layer so as to cover the microcrystalline semiconductor layer;

an amorphous semiconductor layer on and in direct contact with the semiconductor layer; and

a pair of impurity semiconductor layers forming a source region and a drain region, on and in direct contact with the amorphous semiconductor layer,

wherein at least part of each of the pair of impurity semiconductor layers overlaps the gate electrode layer,

wherein at least part of the microcrystalline semiconductor layer is provided in part of a channel,

wherein one of the pair of impurity semiconductor layers overlaps the microcrystalline semiconductor layer, and

wherein the semiconductor layer includes a plurality of crystalline regions existing in a dispersed manner in an amorphous structure.

9. The semiconductor device according to claim 8, wherein the microcrystalline semiconductor layer contains phosphorus.

10. The semiconductor device according to claim 8, wherein each of the plurality of crystalline regions has a grain with an inverted-conical or inverted-pyramidal structure, growing substantially radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer, in a region not reaching the pair of impurity semiconductor layers.

11. The semiconductor device according to claim 8,

wherein the semiconductor layer contains, in the vicinity of an interface with the gate insulating layer, a first impurity element reducing a coordination number of a semiconductor and generating dangling bonds and a second impurity element generating dangling bonds less easily than the first impurity element, and

wherein a concentration of the first impurity element is smaller than that of the second impurity element by one digit.

12. The semiconductor device according to claim 11, wherein the first impurity element is oxygen and the second impurity element is nitrogen.

13. The semiconductor device according to claim 12, wherein the concentration of nitrogen in the semiconductor layer decreases monotonously from a first side in direct contact with the gate insulating layer to a second side in direct contact with the amorphous semiconductor layer.

14. The semiconductor device according to claim 8, wherein the amorphous semiconductor layer is an amorphous silicon layer.

15. A semiconductor device comprising:

a gate insulating layer over a gate electrode layer;

microcrystalline semiconductor layers which are on and in direct contact with the gate insulating layer and overlap the gate electrode layer;

a semiconductor layer over and in direct contact with the gate insulating layer so as to cover the microcrystalline semiconductor layers;

an amorphous semiconductor layer on and in direct contact with the semiconductor layer;

a pair of impurity semiconductor layers forming a source region and a drain region, on and in direct contact with the amorphous semiconductor layer,

wherein at least part of each of the pair of impurity semiconductor layers overlaps the gate electrode layer,

wherein at least parts of the microcrystalline semiconductor layers are provided in part of a channel,

wherein the semiconductor layer includes a plurality of crystalline regions existing in a dispersed manner in an amorphous structure.

16. The semiconductor device according to claim 15, wherein each of the microcrystalline semiconductor layers contains phosphorus.

17. The semiconductor device according to claim 15, wherein each of the plurality of crystalline regions has a grain with an inverted-conical or inverted-pyramidal structure, growing substantially radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer, in a region not reaching the pair of impurity semiconductor layers.

18. The semiconductor device according to claim 15,

wherein the semiconductor layer contains, in the vicinity of an interface with the gate insulating layer, a first impurity element reducing a coordination number of a semiconductor and generating dangling bonds and a second impurity element generating dangling bonds less easily than the first impurity element, and

wherein a concentration of the first impurity element is smaller than that of the second impurity element by one digit.

19. The semiconductor device according to claim 18, wherein the first impurity element is oxygen and the second impurity element is nitrogen.

20. The semiconductor device according to claim 19, wherein the concentration of nitrogen in the semiconductor layer decreases monotonously from a first side in direct contact with the gate insulating layer to a second side in direct contact with the amorphous semiconductor layer.

21. The semiconductor device according to claim 15, wherein the amorphous semiconductor layer is an amorphous silicon layer.

22. A semiconductor device comprising:

a gate insulating layer over a gate electrode layer;

a microcrystalline semiconductor layer which is on and in direct contact with the gate insulating layer and overlaps the gate electrode layer;

a semiconductor layer over and in direct contact with the gate insulating layer so as to cover the microcrystalline semiconductor layer,

an amorphous semiconductor layer on and in direct contact with the semiconductor layer; and

a pair of impurity semiconductor layers forming a source region and a drain region, on and in direct contact with the amorphous semiconductor layer,

wherein at least part of each of the pair of impurity semiconductor layers overlaps the gate electrode layer,

wherein one of the pair of impurity semiconductor layers overlaps the microcrystalline semiconductor layer and the other impurity semiconductor layer does not overlap the microcrystalline semiconductor layer,

wherein at least part of the microcrystalline semiconductor layer is provided in part of a channel, and

wherein the semiconductor layer includes a plurality of crystalline regions existing in a dispersed manner in an amorphous structure.

23. The semiconductor device according to claim 22, wherein the microcrystalline semiconductor layer contains phosphorus.

24. The semiconductor device according to claim 22, wherein each of the plurality of crystalline regions has a grain with an inverted-conical or inverted-pyramidal structure, growing substantially radially in a direction in which the semiconductor layer is deposited, from a position away from an interface between the gate insulating layer and the semiconductor layer, in a region not reaching the pair of impurity semiconductor layers.

25. The semiconductor device according to claim 22,

wherein the semiconductor layer contains, in the vicinity of an interface with the gate insulating layer, a first impurity element reducing a coordination number of a semiconductor and generating dangling bonds and a second impurity element generating dangling bonds less easily than the first impurity element, and

wherein a concentration of the first impurity element is smaller than that of the second impurity element by one digit.

26. The semiconductor device according to claim 25, wherein the first impurity element is oxygen and the second impurity element is nitrogen.

27. The semiconductor device according to claim 26, wherein the concentration of nitrogen in the semiconductor layer decreases monotonously from a first side in direct contact with the gate insulating layer to a second side in direct contact with the amorphous semiconductor layer.

28. The semiconductor device according to claim 22, wherein the amorphous semiconductor layer is an amorphous silicon layer.