Integrated circuit with wireless connection

• US 20090267084A1
• Filed: 04/25/2008
• Published: 10/29/2009
• Est. Priority Date: 04/25/2008
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Barth, Roland, Stecker, Johannes, Bilger, Christoph, Scheideler, Dirk, Walthes, Wolfgang, Gregorius, Peter, Ruckerbauer, Hermann, Bruennert, Michael, Skerlj, Maurizio
• Granted Patent: US 7,928,525 B2
• Time in Patent Office: Days
• US Class Current: 257/80
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 23/48 Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]

Abstract

An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Claims

1. An integrated circuit, comprising:

a device stack including;

a memory device comprising a first wireless coupling element; and

a semiconductor device including a second wireless coupling element;

wherein the first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

2. The integrated circuit according to claim 1, wherein the first and second wireless coupling elements comprise capacitor plates.

3. The integrated circuit according to claim 2, wherein the first and second capacitor plates arranged in an outermost conductive layer of the memory device and the semiconductor device, respectively.

4. The integrated circuit according to claim 1, wherein the first and second wireless coupling elements comprise coils.

5. The integrated circuit according to claim 4, wherein the first and second coils are formed in an outermost conductive layer of the memory device and the semiconductor device, respectively.

6. The integrated circuit according to claim 1, wherein one of the first and second wireless coupling elements is a light emitting element and the other one of the first and second wireless coupling elements is a light receiving element.

7. The integrated circuit according to claim 6, wherein:

the memory device further comprises a third wireless coupling element; and

the semiconductor device further comprises a fourth wireless coupling element arranged face-to-face with the third wireless coupling element with a dielectric layer sandwiched there between, the third wireless coupling element being of a same type as the second wireless coupling element and the fourth wireless coupling element being of the same type as the first wireless coupling element.

8. The integrated circuit according to claim 1, wherein the semiconductor device is a memory device.

9. The integrated circuit according to claim 1, wherein the semiconductor device is one of:

a central processing unit, a memory controller and a memory buffer.

10. The integrated circuit according to claim 1, wherein the memory device and the semiconductor device comprise wired connections for electric power supply.

11. The integrated circuit according to claim 10, wherein the wired connections are at least one of:

bond wires, solder balls and through-hole vias.

12. The integrated circuit according to claim 1, further comprising:

at least one further memory device including a third wireless coupling element;

wherein;

the semiconductor device further comprises a fourth wireless coupling element; and

the third and fourth wireless coupling elements are arranged face-to-face and are configured to provide a further wireless connection between the memory device and the semiconductor device.

13. The integrated circuit according to claim 1, further comprising:

a further memory device stacked on the memory device and including a third wireless coupling element;

wherein;

the memory device wirelessly connected to the semiconductor device further comprises a fourth wireless coupling element; and

the third and fourth wireless coupling elements are arranged face-to-face and are configured to provide a further wireless connection between the memory device wirelessly connected to the semiconductor device and the further memory device.

14. The integrated circuit according to claim 1, wherein the wireless connection is provided by at least one of:

capacitive coupling, inductive coupling and optical coupling.

15. The integrated circuit according to claim 1, further comprising:

a dielectric arranged between the first wireless coupling element and the second wireless coupling element.

16. A method for transferring data between a memory device and a semiconductor device, the method comprising:

transferring data signals between the memory device and the semiconductor device via a wireless connection.

17. The method of claim 16, wherein the wireless connection is provided by at least one of:

capacitive coupling, inductive coupling and optical coupling.

18. A method for manufacturing an integrated circuit, the method comprising:

providing a memory device including a first wireless coupling element;

providing a semiconductor device including a second wireless coupling element; and

stacking the memory device and the semiconductor device such that the first wireless coupling element is arranged face-to-face with the second wireless coupling element.

19. The method according to claim 18, wherein the first and second wireless coupling elements are formed as capacitor plates.

20. The method according to claim 18, wherein the first and second wireless coupling elements are formed as coils.

21. The method according to claim 18, wherein one of the first and second wireless coupling elements is a light emitting element and the other one of the first and second wireless coupling elements is a light receiving element.

22. The method according to claim 18, wherein a dielectric is sandwiched between the memory device and the semiconductor device

23. A computer system, comprising:

an integrated circuit, including;

a device stack comprising;

a memory device with a first wireless coupling element and a semiconductor device with a second wireless coupling element; and

a dielectric arranged between the first and second wireless coupling elements, wherein the first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.