LIGHT EMITTING DIODE CHIP PACKAGE AND METHOD OF MAKING THE SAME

• US 20090267108A1
• Filed: 06/10/2009
• Published: 10/29/2009
• Est. Priority Date: 07/24/2006
• Status: Active Grant

• Current Assignee: Walsin Lihwa Corporation
• Original Assignee: TOUCH MICRO-SYSTEM TECHNOLOGY CORP. (Walsin Lihwa Corporation)
• Inventors: Lin, Hung-Yi, Huang, Kuan-Jui, Kung, Yen-Ting, Tien, She-Fen
• Granted Patent: US 7,732,233 B2
• Time in Patent Office: Days
• US Class Current: 257/99
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/48095 Kinked
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/64 : Heat extraction or cooling elements

Abstract

The LED chip package of the present invention uses a semiconductor substrate as package substrate, which improves heat dissipation. Also, the LED chip package is incorporated with a planarization structure, which renders the LED chip and the substrate a substantially planar surface, thereby making formation of a planar patterned conductive layer possible. Accordingly, serial/parallel electrical connections between light emitting diode chips can be easily implemented by virtue of the planar patterned conductive layer.

Claims

1. A method of fabricating a light emitting diode (LED) chip package, comprising:

providing a package substrate, and forming a plurality of concave chip mounting areas on an upper surface of the package substrate;

forming a lower patterned conductive layer on the upper surface of the package substrate, wherein the lower patterned conductive layer comprises a plurality of first lower patterned conductive layers and a plurality of second lower patterned conductive layers;

providing a plurality of LED chips, each of the LED chips comprising a light emitting layer, a first conductive type doped semiconductor layer disposed on a lower surface of the light emitting layer, and a second conductive type doped semiconductor layer disposed on an upper surface of the light emitting layer;

mounting each of the LED chips within each of the chip mounting areas, and electrically connecting the first conductive type doped semiconductor layer of each of the LED chips to each of the first lower patterned conductive layers of the lower patterned conductive layer;

forming a planarization structure on the package substrate, the lower patterned conductive layer and the LED chips, and forming a plurality of contact holes in the planarization structure, wherein the contact holes partially expose the second conductive type doped semiconductor layer of each of the LED chips and partially expose each of the second lower patterned conductive layers of the lower patterned conductive layer; and

forming an upper patterned conductive layer on the planarization structure and filling the upper patterned conductive layer into the contact holes so that each of the second lower patterned conductive layers of the lower patterned conductive layer and the second conductive type doped semiconductor layer of each of the LED chips are electrically connected via the upper patterned conductive layer.

2. The method of claim 1, wherein the package substrate comprises a semiconductor substrate.

3. The method of claim 1, further comprising forming a plurality of through holes in the package substrate before forming the lower patterned conductive layer on the upper surface of the package substrate, and electrically connecting the lower patterned conductive layer to a lower surface of the package substrate via the through holes.

4. The method of claim 3, wherein the step of forming the through holes in the package substrate comprise:

forming a plurality of upper through holes on the upper surface of the package substrate; and

forming a plurality of lower through holes on the lower surface of the package substrate, wherein the upper through holes and the lower through holes correspond to each other, forming the through holes.

5. The method of claim 4, wherein the step of electrically connecting the lower patterned conductive layer to the lower surface of the package substrate via the through holes comprise:

forming a back patterned conductive layer on the lower surface of the package substrate and filling the back patterned conductive layer into the lower through holes; and

filling the lower patterned conductive layer into the upper through holes and electrically connecting the lower patterned conductive layer to the back patterned conductive layer.

6. The method of claim 4, wherein the upper through holes are formed by an anisotropic wet etching process.

7. The method of claim 6, wherein the chip mounting areas and the upper through holes are formed by the same anisotropic wet etching process.

8. The method of claim 4, wherein the lower through holes are formed by an anisotropic wet etching process.

9. The method of claim 1, wherein the depth of the chip mounting area and the thickness of the LED chip are substantially the same.

10. The method of claim 1, wherein the planarization structure comprises a photosensitive material layer.

11. The method of claim 1, wherein the upper patterned conductive layer comprises a plurality of web electrode patterns corresponding to the chip mounting areas respectively.

12. The method of claim 1, wherein the step of forming the upper patterned conductive layer further comprises electrically connecting the second conductive type doped semiconductor layer of the LED chip of a chip mounting area to the first lower patterned conductive layer of another chip mounting area via the upper patterned conductive layer, so that the two LED chips are electrically connected in series.

13. The method of claim 1, wherein the step of forming the upper patterned conductive layer further comprises electrically connecting the second conductive type doped semiconductor layer of the LED chip of a chip mounting area to the second lower patterned conductive layer of another chip mounting area via the upper patterned conductive layer, so that the two LED chips are electrically connected in parallel.

14. A light emitting diode (LED) chip package, comprising:

a package substrate comprising at least a concave chip mounting area disposed on an upper surface of the package substrate;

a lower patterned conductive layer disposed on the upper surface of the package substrate, wherein the lower patterned conductive layer comprises at least a first lower patterned conductive layer and at least a second lower patterned conductive layer;

at least an LED chip disposed within the chip mounting area, wherein the LED chip comprises a light emitting layer, a first conductive type doped semiconductor layer disposed on a lower surface of the light emitting layer, and a second conductive type doped semiconductor layer disposed on an upper surface of the light emitting layer, and the first conductive type doped semiconductor layer is electrically connected to the first lower patterned conductive layer of the lower patterned conductive layer;

a planarization structure, having a planar surface, disposed on the package substrate, the lower patterned conductive layer and the LED chip, the planarization structure comprising a plurality of contact holes, wherein the contact holes partially expose the second conductive type doped semiconductor layer of the LED chip and partially expose the second lower patterned conductive layer of the lower patterned conductive layer; and

an upper patterned conductive layer disposed on the planarization structure and filled into the contact holes, wherein the second lower patterned conductive layer of the lower patterned conductive layer and the second conductive type doped semiconductor layer of the LED chip are electrically connected via the upper patterned conductive layer.

15. The LED chip package of claim 14, wherein the package substrate comprises a semiconductor substrate.

16. The LED chip package of claim 14, wherein the package substrate further comprises a plurality of through holes disposed outside of the chip mounting area, and the lower patterned conductive layer is electrically connected to a lower surface of the package substrate via the through holes.

17. The LED chip package of claim 16, wherein each of the through holes comprises an upper through hole and a lower through hole corresponding to the upper through hole.

18. The LED chip package of claim 17, wherein the upper through hole and the lower through hole each comprises an outwardly-inclined side wall.

19. The LED chip package of claim 17, wherein the lower surface of the package substrate comprises a back patterned conductive layer filled into the lower through holes, and the lower patterned conductive layer is filled into the upper through holes so as to electrically connect to the back patterned conductive layer.

20. The LED chip package of claim 14, wherein the depth of the chip mounting area and the thickness of the LED chip are substantially the same.

21. The LED chip package of claim 14, wherein the upper patterned conductive layer comprises a web electrode pattern corresponding to the chip mounting area.

22. The LED chip package of claim 14, further comprising another LED chip disposed within another chip mounting area, wherein the second conductive type doped semiconductor layer of the LED chip of a chip mounting area is electrically connected to the first patterned conductive layer of another chip mounting area via the upper patterned conductive layer, so that the two LED chips are electrically connected in series.

23. The LED chip package of claim 14, further comprising another LED chip disposed within another chip mounting area, wherein the second conductive type doped semiconductor layer of the LED chip of a chip mounting area is electrically connected to the second patterned conductive layer of another chip mounting area via the upper patterned conductive layer, so that the two LED chips are electrically connected in parallel.