MOSFET with Integrated Field Effect Rectifier

• US 20090267111A1
• Filed: 04/28/2009
• Published: 10/29/2009
• Est. Priority Date: 09/26/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Lakota Technologies, Inc. (2-Infinity, Inc.)
• Inventors: CORDELL, Richard, ANKOUDINOV, Alexei, RODOV, Vladimir
• Granted Patent: US 8,598,620 B2
• Time in Patent Office: Days
• US Class Current: 257/124
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A modified MOSFET structure comprises an integrated field effect rectifier connected between the source and drain of the MOSFET to shunt current during switching of the MOSFET. The integrated FER provides faster switching of the MOSFET due to the absence of injected carriers during switching while also decreasing the level of EMI relative to discrete solutions. The integrated structure of the MOSFET and FER can be fabricated using N-, multi-epitaxial and supertrench technologies, including 0.25 μm technology. Self-aligned processing can be used.

Claims

1. In a metal oxide semiconductor field effect transistor (MOSFET) structure having a gate, a source, and a drain, wherein the current flow between the source and the drain is controlled by the voltage applied to the gate, the improvement comprising

a field effect rectifier connected between the source and the drain and serving to shunt current therethrough during switching of the MOSFET.

2. The MOSFET structure of claim 1 wherein the MOSFET is a DMOS structure.

3. The MOSFET structure of claim 1 where the MOSFET is a UMOS structure.

4. The MOSFET structure of claim 1 formed using a self-aligned process.

5. The MOSFET structure of claim 1 formed using not greater than 0.25 μ

m processing.

6. The MOSFET structure of claim 1 formed using N-epitaxial processing.

7. The MOSFET structure of claim 1 formed using multi-epitaxial processing.

8. The MOSFET structure of claim 1 formed using supertrench processing.

9. An integrated semiconductor structure comprising

a MOSFET having a gate, a source and a drain, and

a field effect rectifier formed in the same substrate as the MOSFET and connected between the source and the drain of the MOSFET for conducting current during switching of the MOSFET.