MOSFET STRUCTURE WITH GUARD RING

• US 20090267140A1
• Filed: 04/29/2008
• Published: 10/29/2009
• Est. Priority Date: 04/29/2008
• Status: Abandoned Application

• Current Assignee: Force Mos Technology Co., Ltd.
• Original Assignee: Force Mos Technology Co., Ltd.
• Inventors: HSIEH, Fu-Yuan
• Application Number:
  US12/111,797
• Publication Number:
  US 20090267140A1
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure with guard ling, includes: a substrate including an epi layer region on the top thereof a plurality of source and body regions formed in the epi layer; a metal layer including a plurality of metal layer regions which are connected to respective source and body regions forming metal connections of the MOSFET; a plurality of contact metal plugs connected to respective metal layer regions; a plurality of gate structure filled with polysilicon to be formed on top of the epi layer; an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; and a guard ring wrapping around the trench gates with contact metal plug underneath the gate metal layer

Claims

1. A trench MOSFET structure with a guard ring near a termination area for breakdown voltage enhancement, comprising:

a substrate comprising an epi layer region on a top thereof,

a plurality of source and body regions formed in the epi layer;

a metal layer comprising a plurality of metal layer regions which are connected to respective source and body, and trench gate regions forming metal connections of the MOSFET;

a plurality of contact metal plugs connected to respective metal layer regions;

a plurality of gate structure filled with polysilicon formed on top of the epi layer;

an insulating layer deposited on the epi layer formed underneath the metal layer with a plurality of metal contact holes therein for contacting respective source and body regions; and

the guard ring wrapping around the trench gates which have wider trench width than those in active area, and the contact metal plug connecting to the top of the metal layer.

2. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the MOSFET structure comprises a plurality of transistors formed in a N-type doping epi region on the heavily doped N-type substrate.

3. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the MOSFET structure comprises a plurality of transistors formed in a P-type doping epi region on the heavily doped P-type substrate.

4. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the insulating layer is made of silicon dioxide layer or combination of silicon dioxide and silicon nitride layer.

5. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein heavily-doped regions are disposed at the bottoms of the contact plugs.

6. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the gate oxide layer in trench gates is single oxide of which oxide thickness nearly uniform along trench sidewall and bottom.

7. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the gate oxide layer at the bottoms of trench gates has a significant larger thickness than trench sidewall so as to reduce the capacitance of the gate oxide layer.

8. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the metal layer comprises a first metal layer region and a second metal layer region which are both formed on the top of the MOSFET structure to be the source metal, and the gate and field plate metal of the MOSFET respectively;

and the guard ring wrapping around the gates underneath the second metal layer region of the metal layer.

9. The trench MOSFET structure with the guard ring as claimed in claim 8, wherein the gate structure comprises narrow trench gate in active area as the gates of the MOSFET for current conduction and wide trench gate near termination area for trench gate contact to top metal through contact metal plug;

the narrow trench gate is corresponding to the first metal layer region (source metal), and the wide trench gate is corresponding to the second metal layer region (the trench gate and field plate); and

the guard ring wrapping around the wide trench gate underneath the second metal layer region of the metal layer.

10. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the metal layer comprises a first metal layer region, a second metal layer region and the third metal layer which are formed on the top of the MOSFET structure to be the source metal, the gate metal and field plate metal of the MOSFET respectively;

and the guard ring wrapping around the wide trench gates underneath the gate metal layer region of the metal layer.

11. The trench MOSFET structure with the guard ring as claimed in claim 1, wherein the trench gate having contact metal plug is deeper and wider than the other gate.

12. A method for manufacturing a MOSFET structure with a guard ring, comprising the following steps:

providing an epi layer on a heavily doped substrate;

forming a plurality of trenches in the epi layer;

covering a gate oxide layer on sidewalls and a bottom of the trenches;

forming a conductive layer in the trenches to be used as a gate of MOSFET;

forming a guard ring near by termination wrapping around the trench gates, which is used for gate metal contact;

forming a plurality of body and source regions in the epi layer;

forming an insulating layer on the epi layer;

forming a plurality of contact openings in the insulating layer and the source and body regions;

forming contact metal plugs in the contact openings to directly contact with both source and body regions, and a metal layer on the insulating layer.

13. The method as claimed in claim 12, wherein the MOSFET structure comprises a plurality of transistors formed in a N-type doping epi region on the heavily doped N-type substrate.

14. The method as claimed in claim 12, wherein the MOSFET structure comprises a plurality of transistors formed in a P-type doping epi region on the heavily doped P-type substrate.

15. The method as claimed in claim 12, wherein the insulating layer is made of silicon dioxide layer or combination of silicon and silicon nitride layer.

16. The method as claimed in claim 12, wherein heavily-doped regions are disposed at the bottoms of the contact metal plugs.

17. The method as claimed in claim 12, wherein the gate oxide layer in trench gates is single oxide of which oxide thickness nearly uniform along trench sidewall and bottom.

18. The method as claimed in claim 12, wherein the gate oxide layer at the bottoms of trench gates has a significant larger thickness than trench sidewall so as to reduce the capacitance of the gate oxide layer.

19. The method as claimed in claim 12, wherein the metal layer comprises a first metal layer region and a second metal layer region which are both formed on the top of the MOSFET structure to be the source metal, and the gate and field plate metal of the MOSFET respectively;

and the guard ring wrapping around the gates underneath the second metal layer region of the metal layer.

20. The method as claimed in claim 12, wherein the gate structure comprises narrow trench gate in active area as the gates of the MOSFET for current conduction and wide trench gate near termination area for trench gate contact to top metal through contact metal plug. The narrow trench gate is corresponding to the first metal layer region (source metal), and the wide trench gate is corresponding to the second metal layer region (the trench gate and field plate);

and the guard ring wrapping around the wide trench gate underneath the second metal layer region of the metal layer.

21. The method as claimed in claim 12, wherein the metal layer comprises a first metal layer region, a second metal layer region and the third metal layer which are formed on the top of the MOSFET structure to be the source metal, the gate metal and field plate metal of the MOSFET respectively;

and the guard ring wrapping around the wide trench gates underneath the gate metal layer region of the metal layer.

22. The method as claimed in claim 12, wherein the trench gate having contact metal plug is deeper and wider than other gates.