INCREASING BODY DOPANT UNIFORMITY IN MULTI-GATE TRANSISTOR DEVICES
First Claim
1. An apparatus comprising:
- a semiconductor substrate;
a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed;
a dielectric material coupled with the source region and the drain region of the multi-gate fin; and
the subsequent gate structure coupled to the gate region of the multi-gate fin.
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Abstract
Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.
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Citations
20 Claims
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1. An apparatus comprising:
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a semiconductor substrate; a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed; a dielectric material coupled with the source region and the drain region of the multi-gate fin; and the subsequent gate structure coupled to the gate region of the multi-gate fin. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method comprising:
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forming a sacrificial gate structure on a multi-gate fin, the multi-gate fin being coupled with a semiconductor substrate; removing the sacrificial gate structure to expose the multi-gate fin; and body doping the multi-gate fin after removing the sacrificial gate structure. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A system comprising:
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a processor; and a memory coupled with the processor, wherein the processor or the memory, or combinations thereof, comprise one or more multi-gate transistor devices comprising; a semiconductor substrate; a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed; a dielectric material coupled with the source region and the drain region of the multi-gate fin; and the subsequent gate structure coupled to the gate region of the multi-gate fin. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification