PRE-ENCAPSULATED CAVITY INTERPOSER

• US 20090267171A1
• Filed: 05/28/2008
• Published: 10/29/2009
• Est. Priority Date: 04/24/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ai-Chie, Wang, Yean, Tay Wuu
• Granted Patent: US 8,072,082 B2
• Time in Patent Office: Days
• US Class Current: 257/434
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81385 Shape, e.g. interlocking features
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1017 the lowermost container comprising a device support
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1052 Wire or wire-like electrical connections
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/14618 : Containers
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 31/0203 : Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

A pre-encapsulated cavity interposer, a pre-encapsulated frame, for a semiconductor device.

Claims

1. A pre-encapsulated frame comprising:

an encapsulated member having a cavity therein, the cavity having a portion of the encapsulated member extending thereover and another portion extending therearound; and

a plurality of traces located in the encapsulated member, each trace having a first portion extending in the portion of the encapsulated member extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto.

2. The pre-encapsulated frame of claim 1, wherein the one end of the second portion of a trace of the plurality of traces includes at least one of one or more recesses therein and a roughened surface.

3. The pre-encapsulated frame of claim 1, wherein the plurality of traces comprise:

a first plurality of traces having a first portion extending from one side of the encapsulated member across a portion of the cavity; and

a second plurality of traces having a first portion extending from another side of the encapsulated member across a portion of the cavity.

4. The pre-encapsulated frame of claim 3, wherein the plurality of traces further comprise:

a third plurality of traces having a first portion extending from a third side of the encapsulated member across a portion of the cavity.

5. The pre-encapsulated frame of claim 4, wherein the plurality of traces further comprise:

a fourth plurality of traces having a first portion extending from a fourth side of the encapsulated member across a portion of the cavity.

6. The pre-encapsulated frame of claim 1, wherein the second portion of a trace includes two portions exposed from the encapsulated member.

7. The pre-encapsulated interposer frame of claim 1, wherein another end of a trace is exposed for connection thereto.

8. The pre-encapsulated frame of claim 1, wherein the pre-encapsulated interposer frame comprises one of a strip of pre-encapsulated frames.

9. The pre-encapsulated frame of claim 1, wherein the pre-encapsulated frame comprises one of a panel of pre-encapsulated frames.

10. The pre-encapsulated frame of claim 1, further comprising a semiconductor device located in the cavity of the encapsulated member.

11. The pre-encapsulated frame of claim 10, wherein the semiconductor device comprises a flip-chip type semiconductor device.

12. The pre-encapsulated frame of claim 10, wherein the semiconductor device comprises a semiconductor device having at least one bond pad thereof connected to at least one trace using a bond wire.

13. The pre-encapsulated frame of claim 1, wherein the first portion of a trace has a length greater than that of the first portion of another trace.

14. The pre-encapsulated frame of claim 3, wherein the first portion of a trace of the first plurality of traces has a length greater than that of the first portion of a trace of the second plurality of traces.

15. The pre-encapsulated frame of claim 10, wherein the plurality of traces comprise a plurality of traces configured for connection to a semiconductor device having bond pads in a one-sided layout.

16. The pre-encapsulated frame of claim 10, wherein the plurality of traces comprise a plurality of traces configured for connection to a semiconductor device having the bond pads thereof in a 1.5 sided layout.

17. The pre-encapsulated frame of claim 10, wherein the plurality of traces comprise a plurality of traces configured for connection to a semiconductor device having the bond pads thereof in a one sided layout along the long side of the semiconductor device.

18. The pre-encapsulated frame of claim 10, wherein the plurality of traces comprise a plurality of traces configured for connection to a semiconductor device having the bond pads thereof in a two sided layout.

19. The pre-encapsulated frame of claim 10, wherein the plurality of traces comprise a plurality of traces configured for connection to a semiconductor device having the bond pads thereof located essentially in the center of the semiconductor device.

20. The pre-encapsulated frame of claim 10, wherein the plurality of traces comprise a plurality of traces configured for connection to a semiconductor device having the bond pads thereof located essentially in a single row in the center of the semiconductor device.

21. The pre-encapsulated frame of claim 10, wherein the plurality of traces comprise a plurality of traces configured for connection to a semiconductor device having the bond pads thereof located essentially in multiple rows essentially in the center of the semiconductor device.

22. The pre-encapsulated frame of claim 10, further comprising:

encapsulation material located in the cavity of the encapsulated member.

23. The pre-encapsulated frame of claim 1, wherein the one end of the second portion of a trace of the plurality of traces includes one of a groove therein and a roughened surface thereon.

24. The pre-encapsulated frame of claim 1 wherein the second portion of a trace of the plurality of traces comprises a plurality of portions, each portion having one end of the second portion being exposed for connection thereto.

25. The pre-encapsulated frame of claim 1, wherein the cavity of the encapsulated member includes a cavity having a size for more than one semiconductor device to be located therein.

26. A pre-encapsulated assembly comprising:

a first encapsulated member having a cavity therein, the cavity having a portion of the first encapsulated member extending thereover and another portion extending therearound;

a plurality of traces located in the first encapsulated member, each trace having a first portion extending in the portion of the first encapsulated member extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto;

a first semiconductor device located in the cavity of the first encapsulated member;

a second encapsulated member having a cavity therein, the cavity having a portion of the second encapsulated member extending thereover and another portion extending therearound;

a plurality of traces located in the second encapsulated member, each trace having a first portion extending in the portion of the encapsulated member extending over the cavity and a second portion extending in the another portion of the second encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto by the one end of a trace of the plurality of traces of the first encapsulated member; and

a second semiconductor device located in the cavity of the second encapsulated member.

27. The pre-encapsulated assembly of claim 26, wherein the first semiconductor device comprises a NAND semiconductor memory device.

28. The pre-encapsulated assembly of claim 27, wherein the second semiconductor device comprises a DRAM semiconductor memory device.

29. The pre-encapsulated assembly of claim 26, wherein the first semiconductor device comprises a controller semiconductor device.

30. The pre-encapsulated assembly of claim 26, wherein the first semiconductor device comprises one of a controller semiconductor device and a NAND semiconductor memory device and the second semiconductor device comprises one of a NAND semiconductor memory device and a DRAM semiconductor memory device.

31. The pre-encapsulated assembly of claim 26, further comprising:

a substrate having circuits thereon connected to one of the first encapsulated member and the second encapsulated member.

32. A pre-encapsulated assembly comprising:

a first encapsulated member having a cavity therein, the cavity having a portion of the first encapsulated member extending thereover, another portion extending therearound, and an aperture in the top thereof; and

a plurality of traces located in the first encapsulated member, each trace having a first portion extending in the portion of the first encapsulated member extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto.

33. The pre-encapsulated assembly of claim 32, further comprising:

an imaging semiconductor device located in the cavity; and

a transparent member located over the aperture in the first encapsulated member.

34. The pre-encapsulated assembly of claim 33, further comprising:

a second encapsulated member having a cavity therein, the cavity having a portion of the first encapsulated member extending thereover, another portion extending therearound, and an aperture in the top thereof; and

a transparent member located over the aperture in the second encapsulated member.

35. The pre-encapsulated assembly of claim 33, wherein the imaging semiconductor device is connected to at least one of the plurality of traces using a bond wire.

36. The pre-encapsulated assembly of claim 33, wherein the imaging semiconductor device comprises an imaging semiconductor device having flip-chip style connections to the plurality or traces of the encapsulated member.

37. The pre-encapsulated assembly of claim 33, further comprising:

a third encapsulated member having a cavity therein, the cavity having a portion of the encapsulated member extending thereover and another portion extending therearound;

a plurality of traces located in the encapsulated member, each trace having a first portion extending in the portion of the encapsulated member extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto; and

a first semiconductor device located in the cavity.

38. The pre-encapsulated assembly of claim 33, wherein the first semiconductor device comprises one of a controller semiconductor device, a NAND semiconductor memory device, and a DRAM semiconductor memory device.

39. A pre-encapsulated frame comprising:

an encapsulated member having a cavity therein, the cavity having a portion of the encapsulated member extending thereover and another portion extending therearound; and

a plurality of traces located in the encapsulated member, each trace having a first portion extending in the portion of the encapsulated member extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto, the second portion configured for connecting to a first semiconductor device and a second semiconductor device.

40. The pre-encapsulated frame of claim 39, further comprising:

a first semiconductor device connected to a portion of the second portion of a trace of the plurality of traces; and

a second semiconductor device connected to a another portion of a trace of the plurality of traces.

41. The pre-encapsulated frame of claim 40, wherein the first semiconductor device comprises a semiconductor device adhesively attached to a portion of the encapsulated member and the second semiconductor device comprises a semiconductor device adhesively attached to a portion of the first semiconductor device.

42. A pre-encapsulated frame comprising:

an encapsulated member having a cavity therein, the cavity having a portion of the encapsulated member extending thereover and another portion extending therearound; and

a plurality of traces located in the encapsulated member, a first plurality of traces having a first length and a second plurality of traces having a second length, each trace having a first portion extending in the portion of the encapsulated member extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto, the second portion configured for connecting to a first semiconductor device and a second semiconductor device.

43. The pre-encapsulated frame of claim 42, further comprising:

a first semiconductor device connected to the first plurality of traces; and

a second semiconductor device connected to the second plurality of traces.

44. The pre-encapsulated frame of claim 43, further comprising:

an encapsulant material located in the cavity.

45. The pre-encapsulated frame of claim 43, wherein the first semiconductor device comprises a semiconductor device located above the second semiconductor device in the cavity.

46. A method of assembling a pre-encapsulated assembly comprising:

attaching an imaging semiconductor device to an a first encapsulated member having a cavity therein, the cavity having a portion of the first encapsulated member extending thereover, another portion extending therearound, and an aperture in the top thereof and a plurality of traces located in the first encapsulated member, each trace having a first portion extending in the portion of the first encapsulated member extending over the cavity and a second portion extending in the another portion of the encapsulated member connected to the first portion, one end of the second portion being exposed for connection thereto;

dispensing an adhesive contacting a portion of the first encapsulated member and a portion of the imaging semiconductor device;

attaching a transparent member to the first encapsulated member by contacting the adhesive;

sealing the cavity in the encapsulated member using a liquid material; and

placing solder material on the first encapsulated member in a pattern.