Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump

• US 20090267213A1
• Filed: 04/09/2009
• Published: 10/29/2009
• Est. Priority Date: 03/05/2001
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lei, Ming-Ta, Lin, Mou-Shiung, Lin, Chuen-Jye
• Application Number:
  US12/384,977
• Publication Number:
  US 20090267213A1
• Time in Patent Office: Days
• US Class Current: 257/687
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.

Claims

1. A chip package comprising:

a substrate;

a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;

a copper pillar between said first contact point and said substrate, wherein said copper pillar has a height between 10 and 100 micrometers, and wherein said copper pillar is connected to said first contact point through said opening;

a second metal layer between said first contact point and said copper pillar, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said copper pillar is connected to said first contact point through said second metal layer;

a solder between said copper pillar and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said copper pillar; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said copper pillar.

2. The chip package of claim 1 further comprising a nickel-containing layer between said solder and said copper pillar.

3. The chip package of claim 2, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

4. The chip package of claim 1, wherein said second metal layer comprises titanium.

5. The chip package of claim 1, wherein said metal pad comprises copper.

6. The chip package of claim 1, wherein said substrate comprises a solder mask, a second contact point in a channel in said solder mask, a third contact point in said channel, wherein said second contact point is separate from said third contact point, and wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, a first interconnect covered by said solder mask and connected to said second contact point through said first sidewall, and a second interconnect covered by said solder mask and connected to said third contact point through said second sidewall, wherein said solder is joined with said second contact point.

7. A chip package comprising:

a substrate;

a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;

a copper-containing layer between said first contact point and said substrate, wherein said copper-containing layer is connected to said first contact point through said opening;

a second metal layer between said first contact point and said copper-containing layer, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said copper-containing layer is connected to said first contact point through said second metal layer;

a solder between said copper-containing layer and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said copper-containing layer; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said solder.

8. The chip package of claim 7, wherein said second metal layer comprises titanium.

9. The chip package of claim 7, wherein said metal pad comprises copper.

10. The chip package of claim 7, wherein said copper-containing layer has a thickness between 10 and 100 micrometers.

11. The chip package of claim 7, wherein said substrate comprises a solder mask, a second contact point in a channel in said solder mask, a third contact point in said channel, wherein said second contact point is separate from said third contact point, and wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, a first interconnect covered by said solder mask and connected to said second contact point through said first sidewall, and a second interconnect covered by said solder mask and connected to said third contact point through said second sidewall, wherein said solder is joined with said second contact point.

12. A chip package comprising:

a substrate;

a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;

a copper-containing layer between said first contact point and said substrate, wherein said copper-containing layer is connected to said first contact point through said opening;

a second metal layer between said first contact point and said copper-containing layer, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said copper-containing layer is connected to said first contact point through said second metal layer;

a solder between said copper-containing layer and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said copper-containing layer;

a nickel-containing layer between said copper-containing layer and said solder; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said solder.

13. The chip package of claim 12, wherein said second metal layer comprises titanium.

14. The chip package of claim 12, wherein said metal pad comprises copper.

15. The chip package of claim 12, wherein said copper-containing layer has a thickness between 10 and 100 micrometers.

16. The chip package of claim 12, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.

17. A chip package comprising:

a substrate;

a semiconductor device over said substrate, wherein said semiconductor device comprises a silicon substrate, a dielectric layer under said silicon substrate, a first metal layer under said dielectric layer, wherein said first metal layer comprises a metal pad and a metal piece separate from said metal pad and neighboring said metal pad, and a polymer layer under said dielectric layer, under said metal pad, under said metal piece and in a gap between said metal pad and said metal piece, wherein an opening in said polymer layer is under a first contact point of said metal pad, and said first contact point is at a top of said opening;

a nickel-containing layer between said first contact point and said substrate, wherein said nickel-containing layer is connected to said first contact point through said opening;

a second metal layer between said first contact point and said nickel-containing layer, wherein said second metal layer is on said first contact point, on a bottom surface of said polymer layer and in said opening, wherein said bottom surface has a first region directly over said second metal layer and directly under said metal pad and a second region directly under the middle of said gap, wherein said first region is at a substantially same horizontal level as said second region, and there is no significant step between said first region and said second region, and wherein said nickel-containing layer is connected to said first contact point through said second metal layer;

a solder between said nickel-containing layer and said substrate, wherein said solder is joined with said substrate, and wherein said solder is connected to said nickel-containing layer; and

an underfill between said semiconductor device and said substrate, wherein said underfill contacts with said semiconductor device and said substrate and encloses said solder.

18. The chip package of claim 17, wherein said second metal layer comprises titanium.

19. The chip package of claim 17, wherein said metal pad comprises copper .

20. The chip package of claim 17, wherein said nickel-containing layer has a thickness between 1 and 10 micrometers.