BONDED SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING THE SAME

• US 20090267233A1
• Filed: 05/21/2009
• Published: 10/29/2009
• Est. Priority Date: 11/04/1996
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: BeSang Inc.
• Inventors: Lee, Sang-Yun
• Granted Patent: US 8,058,142 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01031 Gallium [Ga]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/0104 Zirconium [Zr]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01093 : Neptunium [Np]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12036 : PN diode
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A bonded semiconductor structure static random access memory circuit includes a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line. The memory circuit includes a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack is coupled to the interconnect region through a bonding interface, and wherein the semiconductor layer stack includes a pn junction.

Claims

1. A bonded semiconductor structure static random access memory circuit, comprising:

a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line; and

a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack is coupled to the interconnect region through a bonding interface, and wherein the semiconductor layer stack includes a pn junction.

2. The circuit of claim 1, further including a conductive bonding layer which extends between the interconnect region and stack of semiconductor layers.

3. The circuit of claim 2, further including a second horizontally oriented transistor carried by the support substrate, wherein the first and second horizontally oriented transistors are in communication with each other through the conductive bonding layer.

4. The circuit of claim 1, wherein a source and control terminal of the first horizontally oriented transistor are in communication with each other through the conductive bonding layer.

5. The circuit of claim 1, wherein the support substrate includes a single substrate well region per SRAM unit cell.

6. The circuit of claim 1, further including the detach region, wherein the detach region includes porous silicon.

7. A method of manufacturing a bonded semiconductor structure static random access memory circuit, comprising:

providing a support substrate which carries a first type of transistor;

providing a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack includes a pn junction;

coupling the semiconductor layer stack to the support substrate through a bonding interface; and

processing the semiconductor layer stack to form a second type of transistor.

8. The method of claim 7, further including providing an interconnect region which is carried by the support substrate, the interconnect region having a conductive line.

9. The method of claim 7, further including providing the first and second types of transistors so they are NMOS and PMOS transistors, respectively.

10. The method of claim 7, further including providing the first and second types of transistors so they are in communication with each other through the bonding interface.

11. The method of claim 7, wherein the first and second types of transistors are horizontally and vertically oriented transistors, respectively.

12. The method of claim 7, further including forming a single substrate well region per SRAM unit cell.

13. The method of claim 7, further including separating the donor substrate from the semiconductor layer stack.

14. A bonded semiconductor structure static random access memory circuit, comprising:

a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line; and

a first mesa structure coupled to the interconnect region through a first bonding interface, wherein the first mesa structure includes a pn junction.

15. The circuit of claim 14, further including a first conductive bonding contact region which extends between the interconnect region and first mesa structure.

16. The circuit of claim 15, further including a second horizontally oriented transistor, wherein the first and second horizontally oriented transistors are connected to the first conductive bonding contact region.

17. The circuit of claim 14, wherein the first mesa structure and first horizontally oriented transistor are in communication with each other through the first bonding interface.

18. The circuit of claim 14, further including a second mesa structure coupled to the interconnect region through a second bonding interface, wherein the second mesa structure includes a pn junction.

19. The circuit of claim 18, further including a second conductive bonding contact region which extends between the interconnect region and second mesa structure.

20. The circuit of claim 14, wherein the support substrate includes a single substrate well region per SRAM unit cell.