Clock Gating System and Method

• US 20090267649A1
• Filed: 04/29/2009
• Published: 10/29/2009
• Est. Priority Date: 04/29/2008
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Saint-Laurent, Martin, Mohd, Bassam Jamil, Bassett, Paul
• Granted Patent: US 7,902,878 B2
• Time in Patent Office: Days
• US Class Current: 326/95
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply

Abstract

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

Claims

1. A clock gating circuit comprising:

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

2. The clock gating circuit of claim 1, wherein the input logic circuit includes a pullup circuit serially coupled via the internal enable node to a pulldown circuit, and further comprising:

a first isolation element configured to selectively prevent the pullup circuit from biasing the internal enable node at a logical high voltage level; and

a second isolation element configured to selectively prevent the pulldown circuit from biasing the internal enable node at a logical low level,

wherein at least one of the first isolation element and the second isolation element is responsive to the gated clock signal.

3. The clock gating circuit of claim 1, wherein the keeper circuit includes a keeper isolation element configured to prevent a logical voltage level change at the internal enable node due to a current flow through the keeper circuit during a delay period associated with the gating element when the input clock signal transitions.

4. The clock gating circuit of claim 1, wherein less than nine transistors toggle with each input clock signal transition.

5. The clock gating circuit of claim 1, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal, and a second terminal coupled to an input logic isolation element;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to the second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

6. The clock gating circuit of claim 5, wherein the first terminal of the first NMOS transistor is coupled to the second terminal of the PMOS transistor via the input logic isolation element.

7. The clock gating circuit of claim 1, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply, a control terminal coupled to receive the gated clock signal, and a second terminal coupled to an input logic isolation element; and

an n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to the second terminal of the PMOS transistor via the input logic isolation element and having a second terminal coupled to a ground, wherein a control terminal of the NMOS transistor is coupled to receive the input clock signal.

8. A system comprising:

a NAND logic circuit having a first input coupled to receive a clock signal and having an output coupled to provide a gated clock signal; and

a keeper circuit coupled to provide an enable signal to a second input of the NAND logic circuit, wherein less than nine transistors but not less than four transistors toggle with each clock signal transition.

9. The system of claim 8, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal, the PMOS transistor having a second terminal coupled to an input logic isolation element;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to the second terminal of the PMOS transistor via the input logic isolation element;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the clock signal.

10. The system of claim 8, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to a second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the clock signal.

11. An apparatus comprising:

a semiconductor device comprising;

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

12. The apparatus of claim 11, integrated in a system-on-chip device.

13. The apparatus of claim 11, wherein the input logic circuit, the keeper circuit, and the gating element are included in a communications device or a computer into which the semiconductor device is integrated.

14. The apparatus of claim 11, wherein not more than four transistors of the input logic circuit, the keeper circuit, and the gating element toggle with each input clock signal transition.

15. The apparatus of claim 11, wherein the keeper circuit comprises:

a first switching element having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal, the first switching element having a second terminal coupled to an input logic isolation element;

a second switching element having a first terminal coupled to the first switching element via the input logic isolation element;

an inverter having an input coupled to the second terminal of the first switching element and further having an output coupled to a control terminal of the second switching element; and

a third switching element having a first terminal coupled to the second switching element and having a second terminal coupled to a ground, wherein a control terminal of the third switching element is coupled to receive the input clock signal.

16. The apparatus of claim 15, wherein:

the first switching element is a p-channel metal-oxide-semiconductor (PMOS) transistor;

the second switching element is a n-channel metal-oxide-semiconductor (NMOS) transistor; and

the third switching element is a second NMOS transistor.

17. The apparatus of claim 11, wherein the keeper circuit comprises:

a first field effect transistor (FET) having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a second FET having a first terminal coupled to a second terminal of the first FET via an input logic isolation element;

an inverter having an input coupled to the second terminal of the first FET and further having an output coupled to a control terminal of the second FET; and

a third FET having a first terminal coupled to the second FET and having a second terminal coupled to a ground, wherein a control terminal of the third FET is coupled to receive the input clock signal.

18. The apparatus of claim 11, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to a second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

19. The apparatus of claim 11, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to a second terminal of the PMOS transistor via an input logic isolation element;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

20. An apparatus comprising:

input logic means for receiving at least one input signal and providing an output coupled to an internal enable node;

keeper means for selectively holding a logical voltage level at the internal enable node, the keeper means including at least one switching element that is responsive to a gated clock signal; and

gating means for generating the gated clock signal, wherein the gating means is responsive to an input clock signal and to the logical voltage level at the internal enable node.

21. The apparatus of claim 20 integrated in a system-on-chip device.

22. The apparatus of claim 20, wherein the apparatus is a semiconductor device integrated into a communications device or a computer.

23. The apparatus of claim 20, wherein the keeper means comprises:

first means for switching having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

second means for switching having a first terminal coupled to a second terminal of the first means for switching;

means for inverting having an input coupled to the second terminal of the first means for switching and further having an output coupled to a control terminal of the first means for switching; and

third means for switching having a first terminal coupled to the first means for switching and having a second terminal coupled to a ground, wherein a control terminal of the second means for switching is coupled to receive the input clock signal.

24. A method comprising:

receiving at least one input signal at an input logic circuit having at least one input and having an output coupled to an internal enable node;

generating a gated clock signal at a gating element that is responsive to an input clock signal and to a logical voltage level at the internal enable node; and

selectively holding the logical voltage level at the internal enable node in response to the gated clock signal.

25. The method of claim 24, wherein receiving the at least one input signal, selectively holding the logical voltage level, and generating the gated clock signal are performed at a processor integrated into an electronic device.

26. The method of claim 24, further comprising selecting one of a first clock gating cell having a first keeper circuit or a second clock gating cell having a second keeper circuit based on at least one design criterion, wherein the first clock gating cell includes fewer transistors that toggle with each input clock signal toggle than the second clock gating cell.

27. The method of claim 26, wherein the at least one design criterion includes power consumption.

28. The method of claim 26, wherein the at least one design criterion includes speed of operation.

29. The method of claim 26, wherein the at least one design criterion includes an area of the first clock gating cell or an area of the second clock gating cell.

30. The method of claim 26, wherein the first clock gating cell includes not more than four transistors that toggle in response to each input clock signal toggle.

31. The method of claim 26, wherein fewer than half of the transistors of the first keeper circuit toggle in response to each input clock signal toggle.

32. The method of claim 26, wherein the first keeper circuit comprises:

a first field effect transistor (FET) having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a second FET having a first terminal coupled to a second terminal of the first FET via an input logic isolation element;

an inverter having an input coupled to the second terminal of the first FET and further having an output coupled to a control terminal of the second FET; and

a third FET having a first terminal coupled to the second FET and having a second terminal coupled to a ground, wherein a control terminal of the third FET is coupled to receive the input clock signal.

33. The method of claim 26, wherein the first keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive a gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to a second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

34. The method of claim 26, wherein the first keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive a gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to a second terminal of the PMOS transistor via an input logic isolation element;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.

35. A method comprising:

a first step for receiving at least one input signal at an input logic circuit having at least one input and an output coupled to an internal enable node;

a second step for generating a gated clock signal at a gating element that is responsive to an input clock signal and to a logical voltage level at the internal enable node; and

a third step for selectively holding the logical voltage level at the internal enable node in response to the gated clock signal.

36. The method of claim 35, wherein the first step, the second step, and the third step are performed by a processor integrated into an electronic device.

37. A computer readable tangible medium storing instructions executable by a computer, the instructions comprising:

instructions that are executable by the computer to provide at least one input signal to an input logic circuit of a clock gating cell to generate a gated clock signal based on the at least one input signal, the input logic circuit having an output coupled to an internal enable node,

wherein the clock gating cell includes a keeper circuit to selectively hold a logical voltage level at the internal enable node using at least one switching element that is responsive to a gated clock signal, and

wherein the clock gating cell includes a gating circuit configured to generate the gated clock signal in response to an input clock signal and to the logical voltage level at the internal enable node.

38. The computer readable tangible medium of claim 37, wherein the instructions are executable by a processor integrated in a communications device or a computer.

39. A method comprising:

receiving design information representing at least one physical property of a semiconductor device, the semiconductor device including;

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal;

transforming the design information to comply with a file format; and

generating a data file including the transformed design information.

40. The method of claim 39, wherein the data file includes a GDSII format.

41. The method of claim 39, further comprising fabricating the semiconductor device according to the transformed design information.

42. A method comprising:

receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising;

an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal; and

a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal; and

transforming the design information to generate a data file.

43. The method of claim 42, wherein the data file has a GERBER format.

44. The method of claim 42, further comprising manufacturing the circuit board configured to receive the packaged semiconductor device according to the transformed design information.

45. The method of claim 44, further comprising integrating the circuit board into a communications device or a computer.

46. A system comprising:

an input logic circuit of a clock gating cell, the input logic having at least one input to receive at least one input signal and having an output coupled to an internal enable node; and

a keeper circuit of the clock gating cell coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal generated at the clock gating cell, wherein the clock gating cell includes not more than four transistors that toggle with each transition of an input clock signal.

47. The system of claim 46, wherein the keeper circuit comprises:

a p-channel metal-oxide-semiconductor (PMOS) transistor having a first terminal coupled to a supply and having a control terminal coupled to receive the gated clock signal;

a first n-channel metal-oxide-semiconductor (NMOS) transistor having a first terminal coupled to a second terminal of the PMOS transistor;

an inverter having an input coupled to the second terminal of the PMOS transistor and further having an output coupled to a control terminal of the first NMOS transistor; and

a second NMOS transistor having a first terminal coupled to the first NMOS transistor and having a second terminal coupled to a ground, wherein a control terminal of the second NMOS transistor is coupled to receive the input clock signal.