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Clock Gating System and Method

  • US 20090267649A1
  • Filed: 04/29/2009
  • Published: 10/29/2009
  • Est. Priority Date: 04/29/2008
  • Status: Active Grant
First Claim
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1. A clock gating circuit comprising:

  • an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;

    a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal; and

    a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

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