PACKAGED SEMICONDUCTOR DEVICE WITH DUAL EXPOSED SURFACES AND METHOD OF MANUFACTURING

• US 20090269885A1
• Filed: 07/09/2009
• Published: 10/29/2009
• Est. Priority Date: 12/30/2005
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Romel N. Manatad, Ruben P. Madrid
• Inventors: Madrid, Ruben P., Manatad, Romel N.
• Granted Patent: US 7,816,178 B2
• Time in Patent Office: Days
• US Class Current: 438/119
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/17051 Bump connectors having different shapes
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84801 Soldering or alloying
• CPC Class Codes: H01L 23/4334 Auxiliary members in encapsulations H01L23/49568 takes precedence
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/84 using a strap connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The invention claimed is a packaged semiconductor device with dual exposed surfaces and a method of manufacturing the device. A thermal clip and one or multiple source pads are exposed on opposite ends of the device through a nonconductive molding material used to package the device. The thermal clip and source pad can be either top or bottom-exposed. The gate, source and drain leads are exposed through the molding material, and all leads are coplanar with the bottom-exposed surface. The device can have multiple semiconductor dies or various sized dies while still having a single, constant footprint. The method of manufacturing requires attaching the semiconductor die to a thermal clip, and then attaching the die with the attached thermal clip to a lead frame. The resulting device is then molded, marked, trimmed and singulated, in this order, creating a packaged semiconductor device with dual exposed surfaces.

Claims

1. A method for making a packaged semiconductor device, the method comprising:

a. providing at least one semiconductor die comprising a transistor having at least one control region and at least one first terminal region and a second terminal region;

b. providing a thermal clip with a first surface and a second surface

c. providing a lead frame array in matrix format, said lead frame comprising at least one first terminal pad structure with at least one first terminal lead extending from one side of said first terminal lead pad structure;

at least one control pad structure with at least one control lead extending from one end of said control pad structure; and

at least one second terminal pad structure with at least one second terminal lead extending from one end of said second terminal pad structure, wherein said lead frame has a first surface and a second surface;

d. providing a nonconductive molding material;

e. attaching said second terminal region of said semiconductor die to said second surface of said thermal clip;

f. attaching said control region of said semiconductor die to said first surface of said control pad structure and said first terminal region to said first surface of said first terminal pad structure in said lead frame;

g. attaching said second surface of said thermal clip to said first surface of said second terminal pad structure in said lead frame;

h. encapsulating said semiconductor die, said thermal clip and said lead frame with said nonconductive molding material, wherein said first surface of said thermal clip and said first terminal pad structure on said second surface of said lead frame and said control lead, said first terminal leads and said second terminal leads are exposed through the molding material.

2. The method of claim 1 further comprising attaching said semiconductor die, said lead frame and said thermal clip by solder paste.

3. The method of claim 2 further comprising using a reflow process prior to encapsulating.

4. The method of claim 3 further comprising marking said device.

5. The method of claim 4 further comprising singulating said device from said lead frame.

6. The method of claim 1 wherein said semiconductor die is a mosfet and said first terminal region is a source region, said control region is a gate region, said second terminal region is a drain region, and wherein said first terminal pad structure and lead are a source pad and lead, said control pad structure and lead are a gate pad and lead, and said second terminal pad structure and lead are a drain pad and lead.

7. The method of claim 1 wherein said semiconductor die is a bipolar transistor and said first terminal region is an emitter region, said control region is a base region, and said second terminal region is a collector region, wherein said base region is disposed between said emitter and collector region, and wherein said first terminal pad structure and lead are an emitter pad and lead, said control pad structure and lead are a base pad and lead, and said second terminal pad structure and lead are a collector pad and lead.