METHODS OF FABRICATING DUAL-DEPTH TRENCH ISOLATION REGIONS FOR A MEMORY CELL
First Claim
1. A method of manufacturing a device structure using a semiconductor layer having a top surface, the method comprising:
- forming a first well of a first conductivity type in the semiconductor layer;
forming first and second deep trench isolation regions in the semiconductor layer that laterally bound a first device region in the first well;
forming a first plurality of doped regions of a second conductivity type and a second plurality of doped regions of the second conductivity type in the first device region;
forming a shallow trench isolation region that extends laterally across the first device region from the first deep trench isolation region to the second deep trench isolation region, the shallow trench isolation region disposed in the first device region between the first plurality of doped regions and the second plurality of doped regions and the shallow trench isolation region extending from the top surface into the semiconductor layer to a first depth such that the first well is continuous beneath the shallow trench isolation region; and
forming a first gate stack on the top surface of the semiconductor layer, the first gate stack configured to control carrier flow between one of the first plurality of doped regions and another of the first plurality of doped regions.
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Abstract
Methods for fabricating dual-depth trench isolation regions for a memory cell. First and second deep trench isolation regions are formed in the semiconductor layer that laterally bound a device region in a well of a first conductivity type in the semiconductor layer. First and second pluralities of doped regions of a second conductivity type are formed in the device region. A shallow trench isolation region is formed that extends laterally across the device region from the first deep trench isolation region to the second deep trench isolation region. The shallow trench isolation region is disposed in the device region between the first and second pluralities of doped regions. The shallow trench isolation region extends into the semiconductor layer to a depth such that the well is continuous beneath the shallow trench isolation region. A gate stack controls carrier flow between a pair of the first plurality of doped regions.
19 Citations
10 Claims
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1. A method of manufacturing a device structure using a semiconductor layer having a top surface, the method comprising:
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forming a first well of a first conductivity type in the semiconductor layer; forming first and second deep trench isolation regions in the semiconductor layer that laterally bound a first device region in the first well; forming a first plurality of doped regions of a second conductivity type and a second plurality of doped regions of the second conductivity type in the first device region; forming a shallow trench isolation region that extends laterally across the first device region from the first deep trench isolation region to the second deep trench isolation region, the shallow trench isolation region disposed in the first device region between the first plurality of doped regions and the second plurality of doped regions and the shallow trench isolation region extending from the top surface into the semiconductor layer to a first depth such that the first well is continuous beneath the shallow trench isolation region; and forming a first gate stack on the top surface of the semiconductor layer, the first gate stack configured to control carrier flow between one of the first plurality of doped regions and another of the first plurality of doped regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification