SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20090269907A1
• Filed: 07/09/2009
• Published: 10/29/2009
• Est. Priority Date: 03/20/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Itoga, Takashi, Takafuji, Yutaka
• Granted Patent: US 7,919,392 B2
• Time in Patent Office: Days
• US Class Current: 438/458
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76259 with separation/delamination along a porous layer
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/8319 Arrangement of the layer connectors prior to mounting
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/26 Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1266 the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01056 : Barium [Ba]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

On an SOI substrate, a hydrogen ion implantation section in which distribution of hydrogen ions peaks in a BOX layer (buried oxide film layer), and a single-crystal silicon thin-film transistor are formed. Then this SOI substrate is bonded with an insulating substrate. Subsequently, the SOI substrate is cleaved at the hydrogen ion implantation section by carrying out heat treatment, so that an unnecessary part of the SOI substrate is removed, Furthermore, the BOX layer remaining on the single-crystal silicon thin-film transistor is removed by etching. With this, it is possible to from a single-crystal silicon thin-film device on an insulating substrate, without using an adhesive. Moreover, it is possible to provide a semiconductor device which has no surface damage and includes a single-crystal silicon thin film which is thin and uniform in thickness.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

bonding a single-crystal silicon substrate with an insulating substrate having a surface on which an SiO₂ film is formed, wherein the single-crystal silicon substrate includes a porous silicon layer and a single-crystal silicon thin film formed on the porous silicon layer and has a surface which is on a single-crystal silicon thin film side with respect to the porous silicon layer and on which an SiO₂ film is formed, a gate insulating film and a gate electrode are formed between the single-crystal silicon thin film and the SiO₂ film on the single-crystal silicon substrate, and the surface of the insulating substrate, where the SiO₂ film is formed, is bonded with the surface of the single-crystal silicon substrate, where the SiO₂ film is formed, and

separating a part of the single-crystal silicon substrate at the porous silicon layer, and removing the porous silicon layer from a remaining part of the single-crystal silicon substrate, the remaining part still being on the insulating substrate after the part is separated.

2. The method as defined in claim 1, wherein, in different regions on the insulating substrate, the single-crystal silicon thin film and a non-single-crystal silicon thin film are formed.

3. The method as defined in claim 1, wherein the single-crystal silicon thin film is not more than about 70 nm thick.

4. The method as defined in claim 1, wherein the single-crystal silicon thin film is not more than about 20 nm thick.

5. The method as defined in claim 1, wherein the non-single-crystal silicon thin film comprises polycrystalline silicon.

6. The method as defined in claim 1, wherein the non-single-crystal silicon thin film comprises continuous grain silicon.

7. The method as defined in claim 1, wherein the non-single-crystal silicon thin film comprises amorphous silicon.

8. The method as defined in claim 1, wherein a non-single crystal silicon thin-film transistor, which includes a gate insulating film comprising at least one insulating film including silicon nitride, is formed using the amorphous silicon thin film.

9. The method as defined in claim 1, wherein a transistor formed using the single-crystal silicon thin film is arranged such that, from an insulating substrate side, a gate electrode, a gate insulating film, and the single-crystal silicon thin film are formed in this order.

10. The method as defined in claim 1, wherein at least a part of the transistor formed using the single-crystal silicon thin film includes an interlayer insulating film and a metal interconnects layer provided further on the single-crystal silicon thin film.

11. The method as defined in claim 1, wherein a transistor formed using the single-crystal silicon thin film is arranged such that, from an insulating substrate side, an interlayer insulating film, a metal interconnects layer, an interlayer insulating film, a gate electrode, a gate insulating film, and the single-crystal silicon thin film are formed in this order, and in at least a part of the transistor, an interlayer insulating film and metal interconnects are further provided on the single-crystal silicon thin film.

12. The method as defined in claim 1, wherein the insulating substrate comprises a high strain point glass including an alkaline-earth alumino-borosilicate glass.

13. The method as defined in claim 1, wherein the insulating substrate comprises any one of a barium borosilicate glass, a barium alumino-borosilicate glass, an alkaline-earth alumino-borosilicate glass, a borosilicate glass, an alkaline-earth-zinc-lead-alumino-borosilicate glass, and an alkaline-earth-lead-alumino-borosilicate glass.

14. The method as defined in claim 1, wherein a difference of linear expansion between the insulating substrate and the single-crystal silicon substrate is about not more than 250 ppm at temperatures in a range between substantially room temperatures and 600°

C.

15. The method as defined in claim 1, wherein the insulating substrate comprises a high strain point glass whose strain point is not less than 500°

C.

16. The method as defined in claim 1, wherein on a substantially entire surface of the insulating substrate, the single-crystal silicon thin film is formed.

17. The method as defined in claim 1, further comprising:

forming a polycrystalline silicon thin film on the insulating substrate in a region different than the single-crystal silicon thin film, the polycrystalline silicon thin film being formed by steps including (i) depositing an SiO₂ film above the entire surface of the insulating substrate, (ii) depositing an amorphous silicon film on the entire surface of the deposited SiO₂ film, and (iii) applying an excimer laser to the amorphous silicon film to form the polycrystalline silicon thin film.

18. The method as defined in claim 1, wherein the separating of a part of the single-crystal silicon substrate at the porous silicon layer comprises cleaving the porous silicon layer by steps including soaking the porous silicon layer with water and then decreasing a temperature of the porous silicon layer to be below 0°

C.

19. The method as defined in claim 1, further comprising:

forming a polycrystalline silicon thin film on the insulating substrate in a region different than the single-crystal silicon thin film, the polycrystalline silicon thin film being formed by steps including (i) depositing an SiO₂ film above the entire surface of the insulating substrate, (ii) depositing an amorphous silicon film on the entire surface of the deposited SiO₂ film, and (iii) applying an excimer laser to the amorphous silicon film to form the polycrystalline silicon thin film.

20. The method as defined in claim 1,

wherein the separating of a part of the single-crystal silicon substrate at the porous silicon layer comprises cleaving the porous silicon layer by steps including soaking the porous silicon layer with water and then decreasing a temperature of the porous silicon layer to be below 0°

C.