NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME

• US 20090269911A1
• Filed: 06/15/2009
• Published: 10/29/2009
• Est. Priority Date: 04/24/2001
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: KATO, Kiyoshi, KUROKAWA, Yoshiyuki
• Granted Patent: US 8,148,215 B2
• Time in Patent Office: Days
• US Class Current: 438/479
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile memory in which a leak current from an electric charge accumulating layer to an active layer is reduced and a method of manufacturing the non-volatile memory are provided. In a non-volatile memory made from a semiconductor thin film that is formed on a substrate (101) having an insulating surface, active layer side ends (110) are tapered. This makes the thickness of a first insulating film (106), which is formed by a thermal oxidization process, at the active layer side ends (110) the same as the thickness of the rest of the first insulating film. Therefore local thinning of the first insulating film does not take place. Moreover, the tapered active layer side ends hardly tolerate electric field concentration at active layer side end corners (111). Accordingly, a leak current from an electric charge accumulating layer (107) to the active layer (105) is reduced to improve the electric charge holding characteristic. As a result, the first insulating film can be further made thin to obtain a high performance non-volatile memory that operates at a low voltage and consumes less power.

Claims

1. A manufacturing method for a semiconductor device including a non-volatile memory, comprising the steps of:

forming a semiconductor film on an insulating surface;

forming a resist pattern over the semiconductor film;

etching the semiconductor film to form a semiconductor island having tapered side edges by decreasing a selective ratio of the semiconductor film and the resist pattern;

forming a first insulating film on the semiconductor island;

forming a floating gate film over a channel forming region of the semiconductor island with the first insulating film interposed therebetween, the floating gate film covering the tapered side edges of the semiconductor island;

forming a second insulating film over the floating gate film; and

forming a control gate film over the floating gate film with the second insulating film interposed therebetween, the control gate film covering the tapered side edges of the semiconductor island.

2. The manufacturing method according to claim 1, wherein the forming the first insulating film is conducted by thermal oxidation of the semiconductor island.

3. The manufacturing method according to claim 1, wherein the forming the first insulating film is conducted by a chemical vapor deposition.

4. The manufacturing method according to claim 1, wherein the selective ratio is decreased continuously during etching.

5. The manufacturing method according to claim 1, wherein CF₄ gas and O₂ gas are used, and a ratio of the O₂ gas is increased continuously during etching.

6. A manufacturing method for an electro-optic device including a non-volatile memory, comprising the steps of:

forming a semiconductor film on an insulating surface;

forming a resist pattern over the semiconductor film;

etching the semiconductor film to form a semiconductor island having tapered side edges by decreasing a selective ratio of the semiconductor film and the resist pattern;

forming a first insulating film on the semiconductor island;

forming a floating gate film over a channel forming region of the semiconductor island with the first insulating film interposed therebetween, the floating gate film covering the tapered side edges of the semiconductor island;

forming a second insulating film over the floating gate film; and

forming a control gate film over the floating gate film with the second insulating film interposed therebetween, the control gate film covering the tapered side edges of the semiconductor island.

7. The manufacturing method according to claim 6, wherein the forming the first insulating film is conducted by thermal oxidation of the semiconductor island.

8. The manufacturing method according to claim 6, wherein the forming the first insulating film is conducted by a chemical vapor deposition.

9. The manufacturing method according to claim 6, wherein the selective ratio is decreased continuously during etching.

10. The manufacturing method according to claim 6, wherein CF₄ gas and O₂ gas are used, and a ratio of the O₂ gas is increased continuously during etching.

11. A manufacturing method for a display device including a non-volatile memory, comprising the steps of:

forming a semiconductor film on an insulating surface;

forming a resist pattern over the semiconductor film;

etching the semiconductor film to form a semiconductor island having tapered side edges by decreasing a selective ratio of the semiconductor film and the resist pattern;

forming a first insulating film on the semiconductor island;

forming a floating gate film over a channel forming region of the semiconductor island with the first insulating film interposed therebetween, the floating gate film covering the tapered side edges of the semiconductor island;

forming a second insulating film over the floating gate film; and

forming a control gate film over the floating gate film with the second insulating film interposed therebetween, the control gate film covering the tapered side edges of the semiconductor island.

12. The manufacturing method according to claim 11, wherein the forming the first insulating film is conducted by thermal oxidation of the semiconductor island.

13. The manufacturing method according to claim 11, wherein the forming the first insulating film is conducted by a chemical vapor deposition.

14. The manufacturing method according to claim 11, wherein the selective ratio is decreased continuously during etching.

15. The manufacturing method according to claim 11, wherein CF₄ gas and O₂ gas are used, and a ratio of the O₂ gas is increased continuously during etching.