METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SEMICIRCULAR TOP SURFACES AND ROUNDED TOP CORNERS AND EDGES

• US 20090269916A1
• Filed: 04/28/2008
• Published: 10/29/2009
• Est. Priority Date: 04/28/2008
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: KANG, Inkuk, MA, Yi, FANG, Shenqing, XUE, Gang, SUGINO, Rinji
• Granted Patent: US 8,987,092 B2
• Time in Patent Office: Days
• US Class Current: 438/587
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Methods for fabricating a FIN structure with a semicircular top surface and rounded top surface corners and edges are disclosed. As a part of a disclosed method, a FIN structure is formed in a semiconductor substrate. The FIN structure includes a top surface having corners and edges. The FIN structure is annealed where the annealing causes the top surface to have a semicircular shape and the top surface corners and edges to be rounded.

Claims

1. A method for forming a FIN structure with semicircular top surface and rounded top surface corners and edges, comprising:

forming a FIN structure in a semiconductor substrate wherein said FIN structure includes a top surface having corners and edges; and

annealing said FIN structure wherein said annealing causes said top surface to have a semicircular shape and said top surface corners and edges to be rounded wherein said annealing causes said top surface to have a semicircular shape and said top surface corners and edges to be rounded without additional operations.

2. The method of claim 1 wherein said FIN structure is associated with the fabrication of an individual charge storage cell.

3. The method of claim 1 wherein said FIN structure is fabricated from a semiconductor wafer.

4. The method of claim 1 wherein said annealing comprises performing a dilute hydrofluoric acid (DHF) clean, an ammonia/peroxide mix (APM) clean and hydrochloric/peroxide mix (HPM) clean to form native oxide and a H2 anneal.

5. The method of claim 1 wherein said annealing is performed at a temperature of 650 to 1100 degrees Celsius.

6. The method of claim 1 wherein said annealing is performed at a pressure of 0.1 Torr to 100 Torr.

7. The method of claim 1 wherein said annealing is performed using an H2 flow of 50 sccm to 20 slm.

8. The method of claim 1 wherein said annealing time is 2 seconds to 600 seconds.

9. A method for forming a storage element, comprising:

forming a FIN structure on a semiconductor substrate wherein said forming said FIN structure comprises;

forming a semiconductor FIN structure wherein said semiconductor FIN structure includes a top surface having corners and edges; and

annealing said semiconductor FIN structure wherein said annealing causes said top surface to have a semicircular shape and said top surface corners and edges to be rounded wherein said annealing causes said top surface to have a semicircular shape and said top surface corners and edges to be rounded without additional operations,

forming a first oxide layer on said semiconductor FIN structure;

forming a charge storage layer on said first oxide layer;

forming a second oxide layer on said charge storage layer; and

forming a polysilicon gate layer on said second oxide layer.

10. The method of claim 9 wherein each of said FIN structures are associated with the fabrication of an individual charge storage cell.

11. The method of claim 9 wherein said FIN structure is formed from a semiconductor wafer.

12. The method of claim 9 wherein said annealing comprises performing a DHF clean to expose a Si surface of said FIN structure, an APM and HPM clean to form native oxide and a H2 anneal.

13. The method of claim 9 wherein said annealing is performed at a temperature of 650 to 1100 degrees Celsius.

14. The method of claim 9 wherein said annealing is performed at a pressure of 0.1 Torr to 100 Torr.

15. The method of claim 9 wherein said annealing is performed using an H2 flow of 50 sccm to 20 slm.

16. The method of claim 9 wherein said annealing time is 2 seconds to 600 seconds.

17. A method for forming a memory array comprising:

forming a semiconductor substrate; and

forming a plurality of storage elements on said semiconductor substrate, comprising;

forming a plurality of semiconductor FIN structures wherein said plurality of semiconductor FIN structures include a top surface having corners and edges; and

annealing the plurality of semiconductor FIN structures wherein said annealing causes said top surface to have a semicircular shape and said top surface corners and edges to be rounded wherein said annealing causes said top surface to have a semicircular shape and said top surface corners and edges to be rounded without additional operations,

forming a first oxide layer on said plurality of semiconductor FIN structures;

forming a charge storage layer on said first oxide layer; and

forming a second oxide layer on the charge storage layer.

18. The method of claim 17 wherein each of said FIN structures are associated with the fabrication of an individual charge storage cell.

20. The method of claim 17 wherein said annealing comprises performing a DHF clean to expose the surface of said FIN structures, an APM and HPM clean to form native oxide and a H2 anneal.

19. (canceled)