Method for fabricating self-aligned complimentary pillar structures and wiring

• US 20090269932A1
• Filed: 04/28/2008
• Published: 10/29/2009
• Est. Priority Date: 04/28/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Radigan, Steven J., Petti, Christopher J., Wang, Chun-Ming, Maxwell, Steven, Chen, Yung-Tin
• Granted Patent: US 7,786,015 B2
• Time in Patent Office: Days
• US Class Current: 438/703
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, selectively removing the spaced apart features, filling a space between a first sidewall spacer and a second sidewall spacer with a filler feature, selectively removing the sidewall spacers to leave a plurality of the filler features spaced apart from each other, and etching the at least one device layer using the filler feature as a mask.

Claims

1. A method of making a semiconductor device, comprising:

forming at least one device layer over a substrate;

forming at least two spaced apart features over the at least one device layer;

forming sidewall spacers on the at least two spaced apart features;

selectively removing the at least two spaced apart features;

filling a space between the sidewall spacers with a plurality of filler features;

selectively removing the sidewall spacers to leave the plurality of filler features spaced apart from each other; and

etching the at least one device layer using the plurality of filler features as a mask;

wherein the at least two spaced apart features comprise a plurality of features; and

wherein the step of forming sidewall spacers comprises forming the sidewall spacers on the plurality of spaced apart features, such that the sidewall spacers on adjacent features along at least two predetermined directions contact each other to form fully enclosed interstitial spaces located between the sidewall spacers.

3. The method of claim 1, further comprising:

filling each space between each two sidewall spacers with one of the plurality of filler features; and

etching the at least one device layer using the plurality of filler features as a mask.

5. The method of claim 1, wherein:

the spaced apart features comprise a first material and the sidewall spacers comprise a second material different from the first material; and

the step of selectively removing the spaced apart features comprises selectively etching the first material of the spaced apart features without substantially removing the second material.

6. The method of claim 1, wherein:

the plurality of filler features comprise a first material and the sidewall spacers comprise a second material different from the first material; and

the step of selectively removing the sidewall spacers comprises selectively etching the second material of the sidewall spacers without substantially removing the first material.

7. The method of claim 1, wherein the step of filling the space between the sidewall spacers with the plurality of filler features comprises forming a filler film over the sidewall spacers and planarizing the filler film to expose upper portions of the sidewall spacers.

8. The method of claim 1, wherein:

the spaced apart features comprise an electrically conductive material covered by a hard mask material;

the plurality of filler features comprise an electrically conductive material; and

the sidewall spacers comprise an electrically insulating material.

9. The method of claim 8, wherein:

the spaced apart features comprise tungsten or amorphous carbon;

the plurality of filler features comprise tungsten; and

the sidewall spacers comprise silicon oxide or silicon nitride.

10. The method of claim 9, wherein the plurality of filler features are retained in a completed device as portions of upper electrodes.

11. The method of claim 9, further comprises removing the plurality of filler features after the step of etching the at least one device layer.

12. The method of claim 1, wherein the step of etching the at least one device layer comprises etching at least one semiconductor device layer to form a plurality of pillar shaped devices.

13. The method of claim 12, wherein the plurality of pillar shaped devices comprise a plurality of diode containing nonvolatile memory cells.

14. The method of claim 12, wherein the spaced apart features have a substantially cylindrical shape and the filler feature has a substantially rectangular or square shape with concave sidewalls.

2. (canceled)

4. (canceled)

15. A method of making a pillar shaped nonvolatile memory device array, comprising:

forming a plurality of bottom electrodes over a substrate;

forming at least one semiconductor device layer over the plurality of bottom electrodes;

forming a plurality of spaced apart features over the at least one semiconductor device layer;

forming a plurality of sidewall spacers on the plurality of spaced apart features;

selectively removing the spaced apart features to leave the plurality of sidewall spacers spaced apart from each other;

forming a filler film over and between the plurality of sidewall spacers;

planarizing the filler film to expose upper portions of the sidewall spacers to leave a plurality of filler features located between the sidewall spacers;

selectively removing the plurality of sidewall spacers to leave the plurality of filler features spaced apart from each other;

etching the at least one semiconductor device layer using the plurality of filler features as a mask to form a plurality of pillar shaped diode containing nonvolatile memory cells; and

forming a plurality of upper electrodes contacting the plurality of nonvolatile memory cells.

16. The method of claim 15, wherein:

the plurality of spaced apart features comprise a first material and the sidewall spacers comprise a second material different from the first material; and

the step of selectively removing the spaced apart features comprises selectively etching the first material of the spaced apart features without substantially removing the second material.

17. The method of claim 15, wherein:

the plurality of filler features comprise a first material and the sidewall spacers comprise a second material different from the first material; and

the step of selectively removing the sidewall spacers comprises selectively etching the second material of the sidewall spacers without substantially removing the first material.

18. The method of claim 15, further comprising removing the filler film from areas outside of the device array boundary.

19. The method of claim 18, further comprising:

providing alignment edge features adjacent to a device array boundary, wherein the alignment edge features have a larger size than the plurality of spaced apart features;

after the step of planarizing the filler film, forming a photoresist layer over the plurality of filler features and over the plurality of spaced apart features;

exposing the photoresist layer using the alignment edge features during alignment;

patterning the exposed photoresist layer to form a photoresist pattern covering a device array area; and

etching the filler film in areas outside of the device array boundary that are not covered by the photoresist pattern.

20-25. -25. (canceled)

26. A method of making a semiconductor device, comprising:

forming at least one device layer over a substrate;

forming at least two spaced apart features over the at least one device layer;

forming sidewall spacers on the at least two spaced apart features;

selectively removing the at least two spaced apart features;

filling a space between the sidewall spacers with a plurality of filler features;

selectively removing the sidewall spacers to leave the plurality of filler features spaced apart from each other; and

etching the at least one device layer using the plurality of filler features as a mask;

wherein;

the spaced apart features comprise an electrically conductive material covered by a hard mask material;

the plurality of filler features comprise an electrically conductive material; and

the sidewall spacers comprise an electrically insulating material.

27. A method of making a semiconductor device, comprising:

forming at least one device layer over a substrate;

forming at least two spaced apart features over the at least one device layer;

forming sidewall spacers on the at least two spaced apart features;

selectively removing the at least two spaced apart features;

filling a space between the sidewall spacers with a plurality of filler features;

selectively removing the sidewall spacers to leave the plurality of filler features spaced apart from each other; and

etching the at least one device layer using the plurality of filler features as a mask;

wherein the step of etching the at least one device layer comprises etching at least one semiconductor device layer to form a plurality of pillar shaped devices; and

wherein the spaced apart features have a substantially cylindrical shape and the filler feature has a substantially rectangular or square shape with concave sidewalls.