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Method for fabricating self-aligned complimentary pillar structures and wiring

  • US 20090269932A1
  • Filed: 04/28/2008
  • Published: 10/29/2009
  • Est. Priority Date: 04/28/2008
  • Status: Active Grant
First Claim
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1. A method of making a semiconductor device, comprising:

  • forming at least one device layer over a substrate;

    forming at least two spaced apart features over the at least one device layer;

    forming sidewall spacers on the at least two spaced apart features;

    selectively removing the at least two spaced apart features;

    filling a space between the sidewall spacers with a plurality of filler features;

    selectively removing the sidewall spacers to leave the plurality of filler features spaced apart from each other; and

    etching the at least one device layer using the plurality of filler features as a mask;

    wherein the at least two spaced apart features comprise a plurality of features; and

    wherein the step of forming sidewall spacers comprises forming the sidewall spacers on the plurality of spaced apart features, such that the sidewall spacers on adjacent features along at least two predetermined directions contact each other to form fully enclosed interstitial spaces located between the sidewall spacers.

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