METHOD AND SYSTEM FOR SINGLE CHIP SATELLITE SET-TOP BOX SYSTEM

• US 20090271828A1
• Filed: 04/28/2009
• Published: 10/29/2009
• Est. Priority Date: 07/11/2003
• Status: Active Grant

• Current Assignee: Paige Bushner
• Original Assignee: Paige Bushner
• Inventors: Bushner, Paige
• Granted Patent: US 8,027,633 B2
• Time in Patent Office: Days
• US Class Current: 725/70
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4263 involving specific tuning arrangements, e.g. two tuners
• CPC Class Codes: H04N 21/42684 Client identification by a unique number or address, e.g. serial number, MAC address, socket ID network arrangements, protocols or services for addressing or naming H04L61/00

Abstract

A system for processing signals is disclosed and may include a single integrated circuit chip. The single integrated circuit chip (SICC) may include one or more processors coupled to a first satellite receiver demodulator and a second satellite receiver demodulator. The SICC may also include one or more video decoders coupled to the one or more processors, and one or more video and graphics display engines coupled to the one or more video decoders. The SICC may further include one or more video encoders coupled to the one or more video and graphics display engines. One or more video digital-to-analog converters and one or more RF modulators may be integrated within the SICC, and the one or more video digital-to-analog converters and the one or more RF modulators may be coupled to the one or more video encoders. The video decoder may include a standard definition MPEG-2 video decoder.

Claims

1-42. -42. (canceled)

43. A system for processing signals, the system comprising:

a single integrated circuit chip, wherein said single integrated circuit chip comprises;

one or more processors coupled to a first satellite receiver demodulator and a second satellite receiver demodulator;

one or more video decoders coupled to said one or more processors;

one or more video and graphics display engines coupled to said one or more video decoders; and

one or more video encoders coupled to said one or more video and graphics display engines.

44. The system according to claim 43, comprising one or more video digital-to-analog converters and one or more RF modulators integrated within said single integrated circuit chip, and said one or more video digital-to-analog converters and said one or more RF modulators are coupled to said one or more video encoders.

45. The system according to claim 43, wherein said one or more video decoder comprises a standard definition MPEG-2 video decoder.

46. The system according to claim 43, comprising one or more audio decoders integrated within said single integrated circuit chip, wherein said one or more audio decoders are coupled to said one or more processors.

47. The system according to claim 46, wherein said one or more audio decoders comprises an MPEG-2 audio decoder.

48. The system according to claim 46, comprising one or more audio digital-to-analog converters integrated within said single integrated circuit chip, wherein said one or more audio digital-to-analog converters are coupled to said one or more audio decoders.

49. The system according to claim 43, comprising one or more memory controllers integrated within said single integrated circuit chip, wherein said one or more memory controllers are coupled to at least said one or more processors.

50. The system according to claim 49, wherein said one or more memory controllers comprises a unified dual data rate DRAM memory controller.

51. The system according to claim 43, comprising a digital satellite equipment control (DiSEqC) bus integrated within said single integrated circuit chip.

52. The system according to claim 43, comprising one or more of a plurality of peripheral interfaces comprising, an infrared interface, a universal asynchronous receiver/transmitter, a serial peripheral interface, a binary synchronous communication interface, general purpose input/output pins, and/or pulse width modulation controller interface, integrated within said single integrated circuit chip.

53. The system according to claim 43, comprising one or more read-only memory integrated within said single integrated circuit chip.

54. The system according to claim 53, wherein said one or more read-only memory comprises a CPU boot ROM and a FLASH.

55. The system according to claim 43, comprising one or more debug ports integrated within said single integrated circuit chip.

56. The system according to claim 55, wherein said debug port comprises a JTAG port or any variation thereof.

57. The system according to claim 43, comprising one or more card reader and/or card writer interfaces integrated within said single integrated circuit chip.

58. The system according to claim 57, wherein said one or more card reader and/or card writer interfaces comprises a smart card reader and/or a smart card writer interface.

59. The system according to claim 43, comprising one or more core voltage regulators integrated within said single integrated circuit chip.

60. The system according to claim 43, comprising one or more phase lock loops integrated within said single integrated circuit chip.

61. The system according to claim 43, comprising one or more telephony modems integrated within said single integrated circuit chip.

62. The system according to claim 43, wherein said first satellite receiver demodulator and said second satellite receiver demodulator comprise one or more of 8 PSK, 8 PSK-turbo and/or QPSK demodulators.

63. A system for processing signals, the system comprising:

one or more circuits integrated within a single integrated circuit chip, said one or more circuits comprising one or more processors, a first satellite receiver demodulator, a second satellite receiver demodulator, one or more video decoders, one or more video and graphics display engines, and one or more video encoders, wherein;

said one or more processors are coupled to said first satellite receiver demodulator and said second satellite receiver demodulator;

said one or more video decoders are coupled to said one or more processors;

said more or more video and graphics display engines are coupled to said one or more video decoders; and

said one or more video encoders are coupled to said one or more video and graphics display engines.

64. The system according to claim 63, wherein said one or more circuits comprises one or more video digital-to-analog converters and one or more RF modulators, and said one or more video digital-to-analog converters and said one or more RF modulators are coupled to said one or more video encoders.

65. The system according to claim 63, wherein said one or more video decoder comprises a standard definition MPEG-2 video decoder.

66. The system according to claim 63, wherein said one or more circuits comprises one or more audio decoders, and said one or more audio decoders are coupled to said one or more processors.

67. The system according to claim 66, wherein said one or more audio decoders comprises an MPEG-2 audio decoder.

68. The system according to claim 66, wherein said one or more circuits comprises one or more audio digital-to-analog converters, and said one or more audio digital-to-analog converters are coupled to said one or more audio decoders.

69. The system according to claim 63, wherein said one or more circuits comprises one or more memory controllers, and said one or more memory controllers are coupled to at least said one or more processors.

70. The system according to claim 69, wherein said one or more memory controllers comprises a unified dual data rate DRAM memory controller.

71. The system according to claim 63, wherein said one or more circuits comprises a digital satellite equipment control (DiSEqC) bus.

72. The system according to claim 63, wherein said one or more circuits comprises one or more of a plurality of peripheral interfaces comprising, an infrared interface, a universal asynchronous receiver/transmitter, a serial peripheral interface, a binary synchronous communication interface, general purpose input/output pins, and/or pulse width modulation controller interface.

73. The system according to claim 63, wherein said one or more circuits comprises one or more read-only memory.

74. The system according to claim 73, wherein said one or more read-only memory comprises a CPU boot ROM and a FLASH.

75. The system according to claim 63, wherein said one or more circuits comprises one or more debug ports.

76. The system according to claim 75, wherein said debug port comprises a JTAG port or any variation thereof.

77. The system according to claim 63, wherein said one or more circuits comprises one or more card reader and/or card writer interfaces integrated within said single integrated circuit chip.

78. The system according to claim 77, wherein said one or more card reader and/or card writer interfaces comprises a smart card reader and/or a smart card writer interface.

79. The system according to claim 63, wherein said one or more circuits comprises one or more core voltage regulators.

80. The system according to claim 63, wherein said one or more circuits comprises one or more phase lock loops.

81. The system according to claim 63, wherein said one or more circuits comprises one or more telephony modems.

82. The system according to claim 63, wherein one or both of said first satellite receiver demodulator and said second satellite receiver demodulator comprise one or more of 8 PSK, 8 PSK-turbo and/or QPSK demodulators.

83. A method for processing information, the method comprising:

performing by one or more processors and/or circuits within a single integrated circuit chip;

receiving a first modulated signal by a first satellite receiver integrated within said single integrated circuit chip;

demodulating said first modulated signal by said first satellite receiver to generate a first demodulated signal;

receiving a second modulated signal by a second satellite receiver integrated within said single integrated circuit chip;

demodulating said second modulated signal by said second satellite receiver within to generate a second demodulated signal;

decoding a video portion of said second demodulated signal to generate a second decoded video signal;

encoding said second decoded video signal to generate a second encoded digital video signal; and

converting said second encoded digital video signal to a second analog video signal.

84. The method according to claim 83, wherein said demodulating of said first modulated signal and said demodulating of said second modulated signal occurs concurrently.

85. The method according to claim 83, comprising decoding by said one or more processors and/or circuits, a video portion of said first demodulated signal to generate a first decoded video signal.

86. The method according to claim 85, comprising encoding by said one or more processors and/or circuits, said first decoded video signal to generate a first encoded digital video signal.

87. The method according to claim 86, comprising converting by said one or more processors and/or circuits, said first encoded digital video signal to a first analog video signal.

88. The method according to claim 83, comprising decoding by said one or more processors and/or circuits, an audio portion of said first demodulated signal to generate a first decoded digital audio signal.

89. The method according to claim 88, comprising converting by said one or more processors and/or circuits, said first decoded digital audio signal to a first analog audio signal.

90. A method for processing information, the method comprising:

performing by one or more processors and/or circuits within a single integrated circuit chip;

receiving a first modulated signal by a first satellite receiver;

demodulating said first modulated signal by said first satellite receiver to generate a first demodulated signal;

receiving a second modulated signal by a second satellite receiver;

demodulating said second modulated signal by said second satellite receiver to generate a second demodulated signal;

decoding a video portion of said second demodulated signal to generate a second decoded video signal;

decoding an audio portion of said second demodulated signal to generate a second decoded digital audio signal; and

converting said second decoded digital audio signal to a second analog audio signal.

91. The method according to claim 90, wherein said demodulating of said first modulated signal and said demodulating of said second modulated signal occurs simultaneously.

92. The method according to claim 91, comprising decoding by said one or more processors and/or circuits, a video portion of said first demodulated signal to generate a first decoded video signal.

93. The method according to claim 92, comprising encoding by said one or more processors and/or circuits, said first decoded video signal within said single integrated circuit chip to generate a first encoded digital video signal.

94. The method according to claim 93, comprising converting by said one or more processors and/or circuits, said first encoded digital video signal to a first analog video signal.

95. The method according to claim 90, comprising decoding by said one or more processors and/or circuits, an audio portion of said first demodulated signal to generate a first decoded digital audio signal.

96. The method according to claim 95, comprising converting by said one or more processors and/or circuits, said first decoded digital audio signal to a first analog audio signal.