FIELD-EFFECT TRANSISTOR

• US 20090272970A1
• Filed: 11/01/2006
• Published: 11/05/2009
• Est. Priority Date: 11/08/2005
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Sano, Masafumi, Kaji, Nobuyuki, Aiba, Toshiaki
• Granted Patent: US 7,851,792 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided is a field-effect transistor including an active layer and a gate insulating film, wherein the active layer includes an amorphous oxide layer containing an amorphous region and a crystalline region, and the crystalline region is in the vicinity of or in contact with an interface between the amorphous oxide layer and the gate insulating film.

Claims

1. A field-effect transistor comprising:

an active layer, and

a gate insulating film,

wherein the active layer comprises an amorphous oxide layer containing an amorphous region and a crystalline region, and the crystalline region is in a vicinity of or in contact with an interface between the amorphous oxide layer and the gate insulating film.

2. A field-effect transistor according to claim 1, wherein the crystalline region is absent in a vicinity of a second interface opposed to a first interface which is the interface between the amorphous oxide layer and the gate insulating film.

3. A field-effect transistor according to claim 1, wherein the amorphous oxide layer is composed of an oxide containing In, Zn and Ga.

4. A field-effect transistor according to claim 1, wherein the amorphous oxide layer has a thickness of 0.05 μ

m or more and 1 μ

m or less.