PIXEL STRUCTURE OF A THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY AND FABRICATING METHOD THEREOF

• US 20090272977A1
• Filed: 07/16/2009
• Published: 11/05/2009
• Est. Priority Date: 08/12/2004
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Huang, Tzufong, HUANG, MAO-TSUN
• Granted Patent: US 7,939,875 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

A method of fabricating a pixel structure of a thin film transistor liquid crystal display is provided. A transparent conductive layer and a first metallic layer are sequentially formed over a substrate. The first metallic layer and the transparent conductive layer are patterned to form a gate pattern and a pixel electrode pattern. A gate insulating layer and a semiconductor layer are sequentially formed over the substrate. A patterning process is performed to remove the first metallic layer in the pixel electrode pattern while remaining the gate insulating layer and the semiconductor layer over the gate pattern. A second metallic layer is formed over the substrate. The second metallic layer is patterned to form a source/drain pattern over the semiconductor layer. A passivation layer is formed over the substrate and then the passivation layer is patterned to expose the transparent conductive layer in the pixel electrode pattern.

Claims

1. A method of fabricating a pixel structure of a thin film transistor liquid crystal display, comprising the steps of:

providing a substrate;

forming a transparent conductive layer and a first metallic layer in sequence over the substrate;

performing a first mask process to pattern the first metallic layer and the transparent conductive layer so as to define a gate pattern and a pixel electrode pattern;

forming a gate insulating layer and a semiconductor layer in sequence over the substrate to cover the gate pattern and the pixel electrode pattern;

performing a second mask process to remove the first metallic layer of the pixel electrode pattern but remaining the gate insulating layer and the semiconductor layer over the gate pattern;

forming a second metallic layer over the substrate;

performing a third mask process to pattern the second metallic layer so as to form a source pattern and a drain pattern over the remained semiconductor layer;

forming a passivation layer over the substrate; and

performing a fourth mask process to pattern the passivation layer so as to expose the transparent conductive layer of the pixel electrode pattern.

2. The method of claim 1, wherein

the first mask process further comprises defining a lower electrode pattern;

the second mask process further comprises remaining the gate insulating layer and the semiconductor layer over the lower electrode pattern; and

the third mask process further comprises remaining the second metallic layer over the semiconductor layer to serve as an upper electrode.

3. The method of claim 1, wherein

the first mask process further comprises defining a bonding pad pattern;

the second mask process further comprises remaining a portion of the gate insulating layer and the semiconductor layer over the bonding pad pattern and removing a portion of the first metallic layer of the bonding pad pattern;

the third mask process further comprises remaining the second metallic layer over the bonding pad pattern; and

the fourth mask process further comprises removing a portion of the passivation layer over the bonding pad pattern.

4. The method of claim 1, wherein

the first mask process further comprises defining a lower electrode pattern and a bonding pad pattern;

the second mask process further comprises remaining the gate insulating layer and the semiconductor layer over the lower electrode pattern and a portion of the bonding pad pattern and removing the first metallic layer in a portion of the bonding pad pattern;

the third mask process further comprises remaining the second metallic layer over the semiconductor layer over the lower electrode pattern to serve as an upper electrode and remaining the second metallic layer over the bonding pad pattern; and

the fourth mask process further comprises removing a portion of the passivation layer over the bonding pad pattern.

5. The method of claim 1, wherein the third mask process further comprises removing a definite thickness from the semiconductor layer located between the source pattern and the drain pattern.

6. The method of claim 1, wherein the first metallic layer comprises a single metallic layer, an alloy layer or a multi-layered metallic layer.

7. The method of claim 1, wherein the second metallic layer comprises a single metallic layer, an alloy layer or a multi-layered metallic layer.

8. A pixel structure of a thin film transistor liquid crystal display, comprising:

a thin film transistor disposed on a surface of a substrate, wherein the thin film transistor comprises a gate pattern, a gate insulating layer disposed on the gate pattern and the substrate, a semiconductor layer covering the gate insulating layer and a source pattern and a drain pattern formed over the semiconductor layer;

a pixel electrode pattern disposed on the surface of the substrate, wherein the pixel electrode pattern is electrically connected to the drain pattern of the thin film transistor;

a passivation layer covering the thin film transistor but exposing the pixel electrode pattern; and

a storage capacitor, disposed on the substrate, comprising a lower electrode, an upper electrode and a capacitor dielectric layer, wherein the lower electrode comprises a lower transparent conductive layer and an upper metallic layer.

9. The pixel structure of claim 8, wherein the drain pattern covers a portion of the pixel electrode pattern.

10. The pixel structure of claim 8, wherein the gate pattern comprises a lower transparent conductive layer and an upper metallic layer.

11. The pixel structure of claim 10, wherein the upper metallic layer comprises a single metallic layer, an alloy layer or a multi-layered metallic layer.

12. The pixel structure of claim 8, wherein the gate insulating layer in the thin film transistor is formed between the semiconductor layer and the gate pattern.

13. The pixel structure of claim 8, wherein the upper electrode covers a portion of the pixel electrode pattern.

14. The pixel structure of claim 8, wherein the pixel structure further comprises a bonding pad pattern disposed on two edges of the substrate.

15. The pixel structure of claim 14, wherein the bonding pad comprises a lower transparent conductive layer and an upper metallic layer, and the upper metallic layer exposes a portion of the lower transparent conductive layer.

16. The pixel structure of claim 14, wherein the passivation layer exposes the lower transparent conductive layer of the bonding pad pattern.

17. The pixel structure of claim 8, wherein the drain pattern and the source pattern are single metallic layers, alloy layers or multi-layered metallic layers.