TRENCH-GATE LDMOS STRUCTURES
First Claim
1. A field effect transistor comprising:
- a first silicon region comprising a body region having a first conductivity type, the first silicon region having a top surface;
a gate-trench region extending from the top surface of the first silicon region into the first silicon region, wherein the gate-trench region has a first sidewall, a bottom, and a second sidewall, the gate-trench region having;
a first gate region including a conductive region; and
an insulating region separating the first gate region from the first sidewall, the bottom, and the second sidewall of the gate-trench region;
a highly-doped drain region of a second conductivity type at the top surface of the first silicon region and contacting a drain electrode, the highly-doped drain region being laterally spaced from the gate-trench region, the second conductivity type being opposite to the first conductivity type;
a lightly-doped drain region of the second conductivity type in the first silicon region, the lightly-doped drain region laterally extending along the top surface of the first silicon region between the second sidewall of the gate-trench region and the highly-doped drain region, and further extending under the bottom of the gate-trench region; and
wherein a portion of the lightly-doped drain region laterally extending along the top surface of the first silicon region extends to a depth shallower than a bottom of the gate-trench region.
7 Assignments
0 Petitions
Accused Products
Abstract
MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias.
-
Citations
20 Claims
-
1. A field effect transistor comprising:
-
a first silicon region comprising a body region having a first conductivity type, the first silicon region having a top surface; a gate-trench region extending from the top surface of the first silicon region into the first silicon region, wherein the gate-trench region has a first sidewall, a bottom, and a second sidewall, the gate-trench region having; a first gate region including a conductive region; and an insulating region separating the first gate region from the first sidewall, the bottom, and the second sidewall of the gate-trench region; a highly-doped drain region of a second conductivity type at the top surface of the first silicon region and contacting a drain electrode, the highly-doped drain region being laterally spaced from the gate-trench region, the second conductivity type being opposite to the first conductivity type; a lightly-doped drain region of the second conductivity type in the first silicon region, the lightly-doped drain region laterally extending along the top surface of the first silicon region between the second sidewall of the gate-trench region and the highly-doped drain region, and further extending under the bottom of the gate-trench region; and wherein a portion of the lightly-doped drain region laterally extending along the top surface of the first silicon region extends to a depth shallower than a bottom of the gate-trench region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A field effect transistor comprising:
-
a first silicon region comprising a body region having a first conductivity type, the first silicon region having a top surface; a gate-trench region extending from the top surface of the first silicon region into the first silicon region, wherein the gate-trench region has a first sidewall, a bottom, and a second sidewall, the gate-trench region having; a first gate region including a first conductive region; a second gate region including a second conductive region, the second gate region located between the top surface of the first silicon region and at least a portion of the first gate region; a first insulating layer between the second gate region and the first sidewall; and a second insulating layer between the second gate region and the second sidewall, the second insulating layer being thicker than the first insulating layer; a highly-doped drain region of a second conductivity type at the top surface of the first silicon region and contacting a drain electrode, the highly-doped drain region being laterally spaced from the gate-trench region, the second conductivity type being opposite to the first conductivity type; a lightly-doped drain region of the second conductivity type in the first silicon region, the lightly-doped drain region laterally extending along the top surface of the first silicon region between the second sidewall of the gate-trench region and the highly-doped drain region, and further extending under the bottom of the gate-trench region; and wherein a portion of the lightly-doped drain region laterally extending along the top surface of the first silicon region extends to a depth shallower than a bottom of the gate-trench region. - View Dependent Claims (10, 11, 12, 13, 14, 15)
-
-
16. A method for forming a field effect transistor, the method comprising:
-
providing a substrate including an epitaxial layer; forming a first trench in the epitaxial layer; filling the first trench with a first insulating layer; forming a second trench in the epitaxial layer adjacent the first insulating layer filling the first trench; lining the second trench with a second insulating layer; at least partially filling the second trench with a first conductive material, and forming a plurality of dopant regions adjacent the first and second trenches, with at least one of the plurality of dopant regions extending under the first and the second trenches. - View Dependent Claims (17, 18, 19, 20)
-
Specification