METHODS OF FORMING ISOLATED ACTIVE AREAS, TRENCHES, AND CONDUCTIVE LINES IN SEMICONDUCTOR STRUCTURES AND SEMICONDUCTOR STRUCTURES INCLUDING THE SAME

• US 20090273051A1
• Filed: 05/05/2008
• Published: 11/05/2009
• Est. Priority Date: 05/05/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Parekh, Kunal R., Zahurak, John K.
• Granted Patent: US 7,989,307 B2
• Time in Patent Office: Days
• US Class Current: 257/506
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.

Claims

1. A method of forming semiconductor structures, the method comprising:

forming a first expendable material on a substrate;

patterning the first expendable material in a first direction on the substrate;

forming a pattern of first spacers on sidewalls of the first expendable material;

removing the first expendable material;

transferring the pattern of first spacers into the substrate;

patterning a second expendable material in a second direction on the substrate;

forming a pattern of second spacers on sidewalls of the second expendable material;

removing the second expendable material; and

transferring the pattern of second spacers into the substrate to form trenches between the second spacers.

2. The method of claim 1, further comprising trimming the first expendable material prior to forming the pattern of first spacers on the sidewalls of the first expendable material.

3. The method of claim 2, further comprising trimming the first expendable material to a sub-lithographic width.

4. The method of claim 1, further comprising filling the trenches with an insulative material.

5. The method of claim 1, wherein the trenches have a sub-lithographic width.

6. A semiconductor structure comprising:

a plurality of silicon pillars in a substrate; and

a plurality of trenches isolating each silicon pillar of the plurality of silicon pillars, wherein at least one of the plurality of trenches or the plurality of silicon pillars has a width of less than 44 nm.

7. The semiconductor structure of claim 6, wherein the width of the each pillar of the plurality of silicon pillars and the width of each trench of the plurality of trenches is less than 44 nm.

8. A method of forming sublithographic trenches in a semiconductor structure, the method comprising:

forming an expendable material on a substrate comprising isolated active areas;

patterning the expendable material;

forming spacers on sidewalls of the expendable material;

forming a sacrificial material adjacent the spacers;

removing the spacers to form a plurality of gaps between the sacrificial material and the expendable material; and

etching the substrate through the plurality of gaps to form a plurality of trenches therein.

9. The method of claim 8, further comprising selecting the expendable material and the sacrificial material to comprise the same material.

10. The method of claim 9, wherein selecting the expendable material and the sacrificial material comprises selecting the expendable material and the sacrificial material from the group consisting of amorphous carbon, transparent carbon, polysilicon, silicon dioxide and silicon nitride.

11. The method of claim 8, wherein etching the substrate through the plurality of gaps to form a plurality of trenches therein comprises forming a plurality of silicon fins in the substrate.

12. The method of claim 8, further comprising forming a plurality of transistors within the plurality of trenches.

13. The method of claim 8, further comprising forming the spacers to have a width of less than a minimum feature size.

14. The method of claim 8, wherein forming a plurality of trenches in the substrate comprises forming a plurality of recessed active device trenches.

15. The method of claim 8, wherein etching the substrate through the plurality of gaps to form a plurality of trenches therein comprises forming the plurality of trenches asymmetrically positioned relative to the isolated active areas.

16. A semiconductor structure comprising a plurality of active areas separated by isolation regions, the plurality of active areas including recessed active device trenches having a width of less than a minimum feature size therein.

17. The semiconductor structure of claim 16, wherein the width of the isolation regions is less than the minimum feature size.

18. The semiconductor structure of claim 16, wherein the width of the plurality of active areas is less than the minimum feature size.

19. The semiconductor structure of claim 16, further comprising a plurality of conductive lines above the plurality of active areas and recessed active device trenches.

20. A method of forming conductive lines on a semiconductor structure, the method comprising:

forming a first expendable material on a substrate comprising isolated active areas and sublithographic gate trenches;

patterning the first expendable material;

forming spacers on sidewalls of the first expendable material;

forming a second expendable material adjacent the spacers, the second expendable material and the first expendable material defining openings over the substrate;

forming a sacrificial material within the openings;

removing the first expendable material and the second expendable material;

forming trenches in the substrate between the spacers and the sacrificial material; and

filling the trenches with a conductive material.

21. The method of claim 20, wherein forming a sacrificial material within the openings comprises forming the sacrificial material over isolation regions adjacent active areas on the substrate.

22. The method of claim 20, wherein forming spacers on sidewalls of the first expendable material comprises forming the spacers substantially vertically aligned with underlying gate trenches in the substrate.

23. The method of claim 20, wherein forming a second expendable material adjacent the spacers comprises depositing the second expendable material on the spacers and trimming the second expendable material to define the openings having a width substantially similar to a width of the spacers.

24. The method of claim 20, further comprising forming the sublithographic gate trenches in the substrate prior to forming a first expendable material on the substrate.

25. The method of claim 20, further comprising forming the isolated active areas on the substrate prior to forming a first expendable material on the substrate, and separating the isolated active areas with isolation regions having a sub-lithographic width.