CONNECTING STRUCTURE FOR FLIP-CHIP SEMICONDUCTOR PACKAGE, BUILD-UP LAYER MATERIAL, SEALING RESIN COMPOSITION, AND CIRCUIT BOARD

• US 20090273073A1
• Filed: 03/28/2008
• Published: 11/05/2009
• Est. Priority Date: 03/30/2007
• Status: Active Grant

• Current Assignee: Sumitomo Bakelite Company Limited
• Original Assignee: Sumitomo Bakelite Company Limited
• Inventors: Hatao, Takuya, Wada, Masahiro, Tachibana, Kenya
• Granted Patent: US 7,893,542 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2201/10977 : Encapsulated connections applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: H05K 3/305 : Affixing by adhesive
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

The invention provides a connecting structure for a flip-chip semiconductor package in which cracking and delamination are inhibited or reduced to improve reliability, and in which the potential range of designs is expanded for the inner circuitry of circuit boards and the inductance is reduced. The invention is a connecting structure for a flip-chip semiconductor package, including: a circuit board having a core layer and at least one build-up layer; a semiconductor element connected via metal bumps to the circuit board; and a sealing resin composition with which gaps between the semiconductor element and circuit board are filled, wherein a cured product of the sealing resin composition has a glass transition temperature between 60° C. and 150° C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/° C. and 35 ppm/° C., a cured product of the build-up layer has a the glass transition temperature of at least 170° C. and a coefficient of linear expansion in the in-plane direction up to the glass transition temperature being not more than 40 ppm/° C., and stacked vias are provided in the build-up layer on at least one side of the core layer.

Claims

1. A connecting structure for a flip-chip semiconductor package, comprising:

a circuit board having a core layer and at least one build-up layer;

a semiconductor element connected via metal bumps to the circuit board; and

a sealing resin composition with which gaps between the semiconductor element and circuit board is filled,

wherein a cured product of the sealing resin composition has a glass transition temperature between 60°

C. and 150°

C. and a coefficient of linear expansion from room temperature to the glass transition temperature being between 15 ppm/°

C. and 35 ppm/°

C.,

a cured product of the build-up layer has a glass transition temperature of at least 170°

C. and a coefficient of linear expansion in the in-plane direction up to the glass transition temperature being not more than 40 ppm/°

C., and

stacked vias are provided in the build-up layer on at least one side of the core layer.

2. The connecting structure for a flip-chip semiconductor package according to claim 1, wherein a resin part of the build-up layer comprises a resin composition including at least one kind selected from the group consisting of epoxy resins, phenol resins, cyanate resins, triazine resins, bismaleimide resins, polyimide resins, polyamide-imide resins, and benzocyclobutene resins.

3. The connecting structure for a flip-chip semiconductor package according to claim 1, comprising build-up layers having stacked vias on both sides of the core layer.

4. The connecting structure for a flip-chip semiconductor package according to claim 1, wherein the core layer has through holes.

5. The connecting structure for a flip-chip semiconductor package according to claim 1, wherein the core layer has through holes layer and the through holes and the semiconductor element are connected through the stacked vias of the build-up layer.

6. The connecting structure for a flip-chip semiconductor package according to claim 1, wherein the stacked vias of the build-up layer are formed on the through holes of the core layer, and the semiconductor element and circuit board are connected by metal bumps through the stacked vias.

7. The connecting structure for a flip-chip semiconductor package according to claim 1, wherein the sealing resin composition comprises at least one epoxy resin, and further comprises a curing agent, silane coupler, and inorganic filler.

8. The connecting structure for a flip-chip semiconductor package according to claim 1, wherein the sealing resin composition has a viscosity of not more than 50 Pa·

sec (25°

C.).

9. A build-up layer material, characterized by being used in the connecting structure for a flip-chip semiconductor package according to claim 1.

10. A sealing resin composition, characterized by being used in the connecting structure for a flip-chip semiconductor package according to claim 1.

11. A circuit board, characterized by being used in the connecting structure for a flip-chip semiconductor package according to claim 1.