System and Method for Providing Adaptive Dead Times

• US 20090273957A1
• Filed: 05/05/2008
• Published: 11/05/2009
• Est. Priority Date: 05/05/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Feldtkeller, Martin
• Granted Patent: US 8,749,209 B2
• Time in Patent Office: Days
• US Class Current: 363/98
• CPC Class Codes: H02M 1/0058 by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/1563 without using an external clock H02M3/158 takes precedence
• CPC Class Codes: H02M 3/33571 Half-bridge at primary side of an isolation transformer
• CPC Class Codes: H02M 7/4815 Resonant converters H02M7/4811 and H02M7/4826 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

System and method for adaptively altering a power supply'"'"'s dead time. A method comprises detecting a start of a dead time, detecting an ending condition of the dead time, and ending the dead time. The detecting of the ending condition is based on a first current flowing through a lower portion of the power supply or a second current flowing through a gate driver of a lower switching element in the power supply.

Claims

1. A method for adaptively controlling a dead time in a half bridge circuit having an upper portion with an upper switching element and a lower portion with a lower switching element, the method comprising:

detecting a start of the dead time;

detecting an ending condition of the dead time, wherein the detecting is based on a first current flowing through a shunt resistor in the lower portion or a second current through a lower gate driver of the lower switching element; and

ending the dead time.

2. The method of claim 1, wherein the detecting the start of the dead time comprises detecting when the upper switching element changes from an ON state to an OFF state with the lower switching element in an OFF state.

3. The method of claim 2, wherein the ending the dead time comprises changing the lower switching element from an OFF state to an ON state.

4. The method of claim 1, wherein the lower switching element and the shunt resistor are serially arranged, wherein the detecting the ending condition of the dead time comprises:

measuring the first current; and

determining the ending condition based on a comparison of the first current and a first threshold.

5. The method of claim 1, wherein the lower switching element and the shunt resistor are serially arranged, wherein the first current comprises a reactive portion and a non-reactive portion, and wherein the detecting the ending condition of the dead time comprises:

measuring a polarity of the first current; and

determining the ending condition in response to a determining that the first current has a polarity that is opposite to a polarity of the non-reactive portion of the first current.

6. The method of claim 1, wherein the upper switching element and the lower switching element are serially arranged, wherein the upper switching element is controlled by an upper gate driver and the lower switching element is controlled by the lower gate driver, wherein the detecting the ending condition of the dead time comprises:

measuring the second current; and

determining the ending condition in response to a determining that the second current is greater than a second threshold, the second threshold having the same polarity as a polarity of the second current required to turn on the lower switching element.

7. A method for adaptively controlling dead time, the method comprising:

adaptively controlling a first dead time;

measuring a duration of the first dead time, wherein the duration is related to an accumulated charge on a capacitor; and

adaptively controlling a second dead time using the duration of the first dead time, wherein the using comprises discharging the accumulated charge on the capacitor.

8. The method of claim 7, wherein the adaptively controlling the first dead time comprises:

detecting a start of the first dead time;

detecting an ending condition of the first dead time; and

ending the first dead time.

9. The method of claim 8, wherein the measuring the duration of the first dead time comprises:

starting an accumulation of the accumulated charge on the capacitor in response to a determining that the first dead time has started; and

stopping the accumulation of the accumulated charge on the capacitor in response to a determining that the ending condition has been detected.

10. The method of claim 9, wherein the adaptively controlling the second dead time comprises:

detecting a start of the second dead time;

discharging the accumulated charge on the capacitor; and

ending the second dead time in response to a determining that the accumulated charge on the capacitor is substantially equal to zero.

11. The method of claim 10, wherein the discharging of the accumulated charge is at substantially the same rate as the accumulation of the accumulated charge.

12. The method of claim 10, wherein the ending the second dead time is in response to a determining that the accumulated charge on the capacitor has discharged to a non-linear point wherein the discharging is no longer substantially linear.

13. The method of claim 12, wherein the ending the second dead time is in response to a determining that the accumulated charge on the capacitor has discharged to a threshold greater than or about equal to the non-linear point.

14. The method of claim 13, wherein the ending the second dead time further comprises delaying the ending the second dead time by a time period substantially equal to a discharging of the charge of the capacitor at the threshold down to substantially zero at a linear discharge rate.

15. The method of claim 9, wherein the ending the first dead time further comprises not ending the first dead time until the accumulated charge on the capacitor has charged to at least a minimum charge.

16. The method of claim 9, wherein the ending the first dead time further comprises ending the first dead time in response to a determining that the accumulated charge on the capacitor has charged to a maximum charge even if the ending condition has not been detected.

17. The method of claim 7, wherein the measuring of the first dead time comprises:

starting a clock signal generator in response to a determining that the first dead time has started;

starting a counter to count periods of a signal generated by the clock signal generator; and

stopping the counter in response to a determining that the ending condition has been detected.

18. An electronic circuit comprising:

a half bridge circuit comprising a first semiconductor switching device and a second semiconductor switching device serially arranged with respect to a first power rail and a second power rail of a power supply, the half bridge circuit configured to selectively couple a load to the power rails of the power supply;

a drive circuit coupled to the half bridge circuit, the drive circuit configured to generate control signals to control the state of the first semiconductor switching device and the second semiconductor switching device; and

a detection circuit coupled to the half bridge circuit and to the drive circuit, the detection circuit configured to measure a value of a first current flowing through a shunt resistor coupled to the second semiconductor switching device or a second current flowing through a gate driver coupled to the second semiconductor switching device, the value to determine the state suitable for zero voltage switching or to indicate a dead time ending condition.

19. The electronic circuit of claim 18, wherein the shunt resistor is coupled between the second semiconductor switching device and the second power rail, the shunt resistor to permit a measuring a current flowing through the second semiconductor switching device.

20. The electronic circuit of claim 19, wherein the detection circuit comprises a first comparator having a first input coupled to the shunt resistor and a second input coupled to a reference value, the comparator to determine when the current has a polarity opposite to a non-reactive portion of a current flowing through the shunt resistor.

21. The electronic circuit of claim 19, wherein the detection circuit comprises a second comparator having a first input coupled to the shunt resistor and a second input coupled to a reference voltage, the comparator to determine when a voltage drop across the shunt resistor is more negative than the reference voltage.

22. The electronic circuit of claim 18, wherein the detection circuit comprises a current detection circuit to compare the second current to a reference value having the same polarity as a polarity of the second current required to turn on the second semiconductor switching device.