Lower power wake-up device

• US 20090275302A1
• Filed: 05/05/2008
• Published: 11/05/2009
• Est. Priority Date: 05/05/2008
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Inventors: Huston, James, Milne, James R.
• Granted Patent: US 8,019,316 B2
• Time in Patent Office: Days
• US Class Current: 455/231
• CPC Class Codes: H04B 1/24 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 52/0245 according to signal strength
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A circuit for producing a wake-up signal to control powering up an electronic system, has a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal. An RF detector detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal. A threshold detector circuit determines if the amplified output signal has reached a predetermined threshold and produces an output signal T. A clock generates a clock signal having clock period in response to the threshold detector output signal T. A data decoder logic circuit turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals. A serial comparator circuit compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Claims

1. A circuit that produces a wake-up signal to control powering up an electronic system, comprising:

a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal;

an RF detector that detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal;

a threshold detector circuit that determines if the amplified output signal has reached a predetermined threshold and produces an output signal T;

a clock that generates a clock signal having clock period in response to the threshold detector output signal T;

a data decoder logic circuit that turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals; and

a serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system.

2. The circuit according to claim 1, wherein the system receives data from the serial comparator and in the presence of a valid data pattern, takes an action specified by the valid data pattern.

3. The circuit according to claim 1, wherein the clock is disabled upon detection by the data decoder of a predetermined number of clock pulses from the clock since the output signal W indicates loss of the RF output signal.

4. The circuit according to claim 1, wherein the clock is disabled after a predetermined number of clock pulses from the clock since loss of the RF output signal.

5. The circuit according to claim 1, wherein the clock is disabled upon detection by the data decoder of an invalid synchronization pattern.

6. The circuit according to claim 1, wherein the output data changes state whenever a specific number of clock pulses occur while the RF output signal is present.

7. The circuit according to claim 1, further comprising at least one additional serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with at least one additional corresponding stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the at least one additional stored synchronization pattern the at least one additional serial comparator circuit generates a wake-up signal that enables power to the electronic system

8. The circuit according to claim 1, wherein the circuit is embodied within a two way radio frequency entertainment system remote controller.

9. The circuit according to claim 1, embodied in a bi-directional home entertainment system remote controller device.

10. The circuit according to claim 1, embodied in a remote control circuit in a home entertainment electronic device.

11. A circuit that produces a wake-up signal to control powering up an electronic system, comprising:

a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal;

an RF detector that detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal;

a threshold detector circuit that determines if the amplified output signal has reached a predetermined threshold and produces an output signal T;

a clock that generates a clock signal having clock period in response to the threshold detector output signal T;

a data decoder logic circuit that turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals;

a serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system; and

wherein the clock is disabled either after a predetermined number of clock pulses from the clock since loss of the RF output signal or upon detection by the data decoder of a predetermined number of clock pulses from the clock since the output signal W indicates loss of the RF output signal, or upon detection by the data decoder of an invalid synchronization pattern.

12. The circuit according to claim 11, wherein the system receives data from the serial comparator and in the presence of a valid data pattern, takes an action specified by the valid data pattern.

13. The circuit according to claim 11, wherein the output data changes state whenever a specific number of clock pulses occur while the RF output signal is present.

14. The circuit according to claim 11, further comprising at least one additional serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with at least one additional corresponding stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the at least one additional stored synchronization pattern the at least one additional serial comparator circuit generates a wake-up signal that enables power to the electronic system

15. The circuit according to claim 11, wherein the circuit is embodied within a two way radio frequency entertainment system remote controller.

16. The circuit according to claim 11, embodied in a bi-directional home entertainment system remote controller device.

17. The circuit according to claim 11, embodied in a remote control circuit in a home entertainment electronic device.

18. A circuit that produces a wake-up signal to control powering up an electronic system, comprising:

a frequency selective radio frequency (RF) amplifier circuit that amplifies signals within a predetermined frequency range and produces an amplified RF output signal;

an RF detector that detects the presence of amplified RF output at the output of the amplifier circuit and produces a signal W indicative of the instantaneous presence of the RF output signal;

a threshold detector circuit that determines if the amplified output signal has reached a predetermined threshold and produces an output signal T;

a clock that generates a clock signal having clock period in response to the threshold detector output signal T;

a data decoder logic circuit that turns off the clock in the absence of an RF output signal for a prescribed time period and decodes the RF detector output signal W into a stream of output signals;

a serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with a stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the stored synchronization pattern the serial comparator circuit generates a wake-up signal that enables power to the electronic system;

wherein the system receives data from the serial comparator and in the presence of a valid data pattern, takes an action specified by the valid data pattern; and

wherein the output data changes state whenever a specific number of clock pulses occur while the RF output signal is present.

19. The circuit according to claim 18, wherein the clock is disabled upon detection by the data decoder of a predetermined number of clock pulses from the clock since the output signal W indicates loss of the RF output signal.

20. The circuit according to claim 18, wherein the clock is disabled after a predetermined number of clock pulses from the clock since loss of the RF output signal.

21. The circuit according to claim 18, wherein the clock is disabled upon detection by the data decoder of an invalid synchronization pattern.

22. The circuit according to claim 18, further comprising at least one additional serial comparator circuit that compares a most recent stream of N output data signals from the data decoder logic circuit with at least one additional corresponding stored reference pattern, wherein when the most recent stream of N output logic signals from the data decoder logic circuit matches the at least one additional stored synchronization pattern the at least one additional serial comparator circuit generates a wake-up signal that enables power to the electronic system

23. The circuit according to claim 18, wherein the circuit is embodied within at least one of a two way radio frequency entertainment system remote controller, a bi-directional home entertainment system remote controller device, and a remote control circuit in a home entertainment electronic device.