CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM

• US 20090276609A1
• Filed: 04/30/2008
• Published: 11/05/2009
• Est. Priority Date: 04/30/2008
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Scott, Jeffrey W., Moyer, William C.
• Granted Patent: US 7,814,300 B2
• Time in Patent Office: Days
• US Class Current: 712/220
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/38 Concurrent instruction execution, e.g. pipeline or look ahead
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3875 Pipelining a single stage, e.g. superpipelining

Abstract

A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

Claims

1. A method, comprising:

providing a data processor having an instruction pipeline, wherein the instruction pipeline has a plurality of instruction pipeline stages, and wherein the plurality of instruction pipeline stages comprise a first instruction pipeline stage and a second instruction pipeline stage;

providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction;

performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected; and

performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

2. A method as in claim 1, further comprising:

providing a memory having a plurality of modes, wherein the plurality of modes comprise the first mode and the second mode.

3. A method as in claim 1, wherein the first mode comprises a parity protected mode.

4. A method as in claim 1, wherein the second mode comprises an error correction code (ECC) protected mode.

5. A method as in claim 1, wherein the first set of computational operations comprises an integer operation.

6. A method as in claim 1, wherein if the first mode has been selected and execution of the first set of computational operations occurs in the first instruction pipeline stage, the data processor instruction has a first latency, and wherein if the second mode has been selected and execution of the first set of computational operations occurs in the second instruction pipeline stage, the data processor instruction still has the first latency.

7. A method as in claim 1, further comprising:

providing a second data processor instruction that causes the data processor to perform a second set of computational operations during execution of the second data processor instruction; and

using both the first instruction pipeline stage and the second instruction pipeline stage when performing the second set of computational operations during execution of the second data processor instruction.

8. A method as in claim 7, wherein execution of the second data processor instruction uses both the first instruction pipeline stage and the second instruction pipeline stage regardless of whether the first mode or the second mode is selected.

9. A method as in claim 7, wherein a number of pipeline stalls due to a data-dependent instruction on a load remains unchanged regardless of whether the first mode or the second mode is selected.

10. A method as in claim 1, further comprising:

providing a storage circuit for storing a value, wherein the value determines whether the first mode or the second mode is selected.

11. A system, comprising:

a processor comprising a pipeline, wherein the pipeline comprises;

a plurality of pipeline stages, wherein the plurality of pipeline stages comprise a prior pipeline stage and a subsequent pipeline stage;

feedforward logic to provide computational results obtained from the subsequent pipeline stage to the prior pipeline stage; and

feedforward control circuitry which selects a first set of feedforward control values to provide to the feedforward logic during execution of a first data-dependent instruction if a first mode has been selected, and which selects a second set of feedforward control values to provide to the feedforward logic during execution of the first data-dependent instruction if a second mode has been selected, wherein the first set of feedforward control values and the second set of feedforward control values are different.

12. A system as in claim 11, wherein the prior pipeline stage performs a first set of computational operations if the first data-dependent instruction is being executed and the first mode has been selected, and wherein the subsequent pipeline stage performs the first set of computational operations if the first data-dependent instruction is being executed and the second mode has been selected.

13. A system as in claim 12, wherein if the first mode has been selected and execution of the first set of computational operations occurs in the prior pipeline stage, the first data-dependent instruction has a first latency, and wherein if the second mode has been selected and execution of the first set of computational operations occurs in the subsequent pipeline stage, the first data-dependent instruction still has the first latency.

14. A system as in claim 12, wherein the first set of computational operations comprises an integer operation.

15. A system as in claim 11, further comprising:

a memory having a plurality of modes, wherein the plurality of modes comprise the first mode and the second mode.

16. A system as in claim 11, wherein the first mode comprises a parity protected mode.

17. A system as in claim 11, wherein the second mode comprises an error correction code (ECC) protected mode.

18. A system as in claim 11, wherein the data processor performs a second set of computational operations during execution of a second data-dependent instruction, and wherein both the prior pipeline stage and the subsequent pipeline stage are used when performing the second set of computational operations during execution of the second data-dependent instruction regardless of whether the first mode or the second mode is selected.

19. A method, comprising:

providing a data processor having an instruction pipeline, wherein the instruction pipeline has a plurality of instruction pipeline stages, and wherein the plurality of instruction pipeline stages comprise a first instruction pipeline stage and a second instruction pipeline stage;

providing a load instruction;

providing a data-dependent instruction;

executing the data-dependent instruction in the first instruction pipeline stage if a most recently executed instruction was the load instruction and if the most recently executed instruction was aligned; and

executing the data-dependent instruction in the second instruction pipeline stage if the most recently executed instruction was the load instruction and if the most recently executed instruction was misaligned and if a first mode is selected.

20. A method as in claim 19, further comprising:

executing the data-dependent instruction in the first instruction pipeline stage if the most recently executed instruction was the load instruction and if the most recently executed instruction was misaligned and if a second mode is selected.