STRUCTURE FOR SEMICONDUCTOR POWER DISTRIBUTION AND CONTROL

• US 20090276644A1
• Filed: 05/02/2008
• Published: 11/05/2009
• Est. Priority Date: 05/02/2008
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Twombly, Peter A., Goodnow, Kenneth J., Shuma, Stephen G.
• Application Number:
  US12/114,038
• Publication Number:
  US 20090276644A1
• Time in Patent Office: Days
• US Class Current: 713/310
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3246 by software initiated power-off
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A design structure for dynamic integrated circuit power distribution and control is disclosed. The design structure includes an external power consumption target generator configured to generate a power dissipation target for one or more integrated circuits. The design structure also includes a first integrated circuit that includes an IC power control unit coupled to the external power consumption target generator. The first integrated circuit also includes a first plurality of functional units, each functional unit of the first plurality including a unit power level control and a first power control grid coupling the IC power control unit to one or more of the first plurality of functional units. The IC power control unit is configured to generate a mode control signal which places at least one of plurality of functional units into a first mode of operation based upon the power consumption target.

Claims

1. A design structure embodied in a machine readable medium, the design structure comprising:

an external power consumption target generator configured to generate a power dissipation target for one or more integrated circuits;

a first integrated circuit including;

an IC power control unit coupled to the external power consumption target generator;

a first plurality of functional units, each functional unit of the first plurality including a unit power level control; and

a first power control grid coupling the IC power control unit to one or more of the first plurality of functional units;

wherein the IC power control unit is configured to generate a mode control signal which places at least one of plurality of functional units into a first mode of operation based upon the power consumption target.

2. The design structure of claim 1 further comprising:

second integrated circuit including;

a second IC power control unit coupled to the external power consumption target generator;

a second plurality of functional units, each functional unit of the second plurality including a unit power level control; and

a second power control grid coupling the IC power control unit to one or more of the plurality of functional units;

wherein the second IC power control unit is configured to generate a mode control signal which places at least one of plurality of functional units into a first mode of operation based upon the power consumption target.

3. The design structure of claim 1, wherein the IC power control unit includes a table including operating modes for one or more of the first plurality of functional units and a power dissipated by each operating mode.

4. The design structure of claim 3, wherein the IC power control unit is configured to generate the mode control signal based upon information contained in the table and the power consumption target.

5. The design structure of claim 3, wherein the table is generated at power on of the system.

6. The design structure of claim 1, wherein the first integrated circuit further includes:

a second power control grid coupled to the IC power control unit and one or more of the first plurality of functional units.

7. The design structure of claim 1, wherein the unit power level control includes:

a uniquely addressable receiver configured to allow communication between the IC power control unit and a particular one of the first plurality of functional units.

8. The design structure of claim 7, wherein the power level control further includes:

a power measuring device configured to determine the power being dissipated at a particular time.

9. The design structure of claim 1, wherein the design structure comprises a netlist.

10. The design structure of claim 1, wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits.

11. The design structure of claim 1, wherein the design resides in a programmable gate array.